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The impact of Rapid Thermal Anneal (RTA) temperature uniformity, ramp-up and cool-down rates on device parameters is a key issue that affects the manufacturability of the process. An L9 with center point designed experiment for RTA Source/Drain (S/D) anneal process parameters was done to characterize the process window for a 0.25 micrometer complementary poly CMOS process. The steady state RTA temperature was varied by plus or minus 20 degrees Celsius around the center point, the ramp-up rates varied from 60 to 110 degrees Celsius/sec, and the cool-down rates were varied by changing the cool-down N2 flow. The N-ch Vt was found to vary by 20 mV with the steady state temperature variation, 20 mV with the ramp up rate and had no dependence on the cool- down rate. The P-ch Vt was found to vary by 25 mV with the steady state temperature, and had no significant dependence on the ramp up or cool-down rate. The drive current and sub- threshold leakage variation for both types of devices tracked the Vt variation. No significant boron penetration was observed at the highest RTA temperature as evidenced by a tight P-Ch Vt distribution. The junction leakages were found to be reduced with higher RTA temperature, perhaps due to slightly deeper junctions. Over-all, the variation in the key device parameters was very small compared to the worst to best case variation allowed in the SPICE model. This establishes the robustness of the device design against variations in RTA parameters.
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