This PDF file contains the front matter associated with SPIE Proceedings Volume 13273, including the Title Page, Copyright information, Table of Contents, and Conference Committee information.

Nanoimprint lithography (NIL) is a high throughput, high-resolution parallel patterning method in which a surface pattern of an imprint mask is replicated into a material by mechanical contact and 3D material displacement. This can be done by shaping a liquid followed by a curing process for hardening, by variation of the thermomechanical properties of a film by UV exposure, heating and cooling or by any other kind of shaping process using the difference in hardness of a mold and a moldable material. The local thickness contrast of the resulting thin molded film can be used as a means to pattern an underlying substrate on wafer level by standard pattern transfer methods, but also directly in applications where a bulk modified functional layer is needed. NIL possesses other important advantages over conventional photolithography and other NGL techniques since it does not require expensive projection optics, advanced illumination sources, or specialized resist materials that are central to the operation of these technologies. Therefore, it is mainly aimed towards fields in high-end photolithography that are costly and do not provide sufficient resolution at reasonable costs. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. The purpose of this paper is to review the performance improvements in NIL and describe how the advances can be applied to a variety of different devices and applications. In terms of NIL performance, we will show the improvements in overlay, defectivity and throughput, and introduce the key advances in methods to enhance automation and productivity. Regarding cross matched machine overlay (XMMO) between ArFi and NIL using an FPA-1200NZ2C, the average mean plus 3 sigma variations was 2.4nm and 2.2nm in x and y, respectively. The best results were on the order of 2.2nm and 2.1nm. Their impact on edge placement error is also discussed Regarding defectivity, random defects have been reduced to a level of less than 0.03 defects/cm² over a period of five months. With respect to applications, three different examples are presented that are related to advanced semiconductor devices are discussed. Logic devices have many metal levels that can benefit from a simpler approach for damascene structures. In this work, we discuss electrical test results at half pitches down to 24nm. DRAM devices also require backend metal processes that currently employ complex cutting layers to make the dense line patterns function correctly. These layers are challenging from both a resolution and pattern placement perspective. The results of a straightforward cut approach using NIL will be discussed. Finally, the combination of NIL and directed self-assembly is introduced as a means for reducing linewidth roughness to ~ 1nm.

0.33 Numerical Aperture [NA) EUV Lithography has been introduced in high volume manufacturing since the beginning of this decade. This was initiated by the logic foundries at the 7nm technology node, focusing on a few layers in the back-end-of-line. In the following nodes, more layers were converted to EUV but very soon also EUV double patterning became necessary. The logic step to avoid double patterning was to increase the NA from 0.33 to 0.55.

Although EUV resists and masks are being used in production today, further patterning infrastructure improvements are mandatory to enable High Volume Manufacturing [HVM] with high NA EUV. In this presentation, the preparations for EUV resists, EUV underlayers, EUV metrology, EUV masks and pellicles will be explained and their readiness assessed.

This paper presents the optimization of the grayscale photolithography mask design through a deep-learning workflow, in particular the training dataset optimization thanks to binarization-based mask generation method is studied. To do that, the dithering approach, the new barycentric approach are investigated along with the impact of dataset composition in terms of 3D shapes and mask chromium pattern. The evaluation method to know which dataset provide the best learning ability and at the end 3D shapes close to the targets shapes is presented. Finally, this paper shows that an optimized dataset composed of heterogeneous shapes and mask generated through the proposed barycentric approach giving good results in terms of obtained 3D shape at the end of the workflow in comparison to the homogeneous dataset. Moreover, thanks to these optimized datasets, the obtained 3D shapes at the end of the deep learning workflow is comparable to physics-based mask design method for objects like hemispheres.

The high spatial resolution of EUV lithography makes it highly sensitive to defects caused by particle contamination on the surface of the mask and the wafer. These particles can degrade imaging quality, cause defects, and ultimately lead to yield loss. This paper investigates the effect of common particle types (BN, SiO₂, and C) on the printed image under different conditions. It focuses on determining the range of particle sizes relevant for pattern defectivity for a set of typical use cases (dense line/spaces and dense hexagonal contact holes) in 0.33NA and 0.55NA (high-NA) EUV lithography scanners. The ultimate objective is to provide guidelines to prevent unnecessary mask cleaning and facilitate wafer and mask inspection. The study is conducted by modeling the EUV scanners and conducting rigorous electromagnetic field (EMF) simulations using the lithography simulator HyperLith™ by Panoramic Technology.

This paper addresses the development and modeling of a novel negative-tone photoresist, the Multi-Trigger Resist (MTR), aimed at enhancing extreme ultraviolet (EUV) lithography. The primary objectives are to create a stochastic model of the photoresist process flow and to analyze the behavior of MTR under various conditions. The model incorporates statistical fluctuations in photon distribution, secondary electron generation, and molecular distribution within the photoresist. Calibration with experimental data demonstrates the model’s capability in predicting critical dimension (CD), line width roughness (LWR), and dose-to-size (DtS) metrics. Results indicate that higher MTR loading and quencher addition improve performance consistency. Further investigation into different exposure types, electron blur lengths, and photoresist absorbance coefficients reveals the intricate balance required for optimizing lithographic outcomes. The findings underscore the model’s utility in guiding the design of next-generation photoresists and highlight areas for future research, including the expansion of calibration datasets and the application to various lithographic features.

In the past decades, the necessity for 3D components became none to be questioned in numerous fields. With these 3D components come new challenges. As an example, the performance of Fabry-Perot based optical filtering devices is dependent on the quality of its sidewalls definition. In this study, we are investigating the mask data preparation method for the patterning of staircase structures thanks to grayscale photolithography. Such structures are used as multiple Fabry-Perot cavities in the context of multispectral imaging. Grayscale photolithography is considered for its offer in 3D micro-fabrication at high throughput. First off, the sidewalls horizontal spread is studied through simulations for different configurations. Metrics are defined and proposed to evaluate the quality of transitions. Secondly, three mask data preparation method are studied : a numerical optimization algorithm as well as an image-to-image deep-learning based workflow are first shown to not meet our application morphological needs. In response, a third method is proposed and is based on local sizings libraries. The recourse to this strategy is shown to have great potential for an improvement of the sidewalls behaviour. However, this methodology taking its first steps, its performance is not pushed to the limit in its current state. As a result, a full mask data preparation flow applied to staircase structures is proposed in the perspectives of this work. With this study we illustrated the importance of the photomask design strategy for the fine tuning of 3D structures sidewalls. We showed the possibility, using a smart mask construction strategy, to produce application-wise enhanced vertical transitions and open the door to further studies toward even steeper sidewalls.

In the rapidly advancing field of microelectronics, accurate and non-destructive 3D metrology is crucial for both advanced nodes and More-than-Moore devices. We propose a novel strategy utilizing Scanning Electron Microscopy (SEM) to achieve fast and non-destructive topographical measurements of microscopic objects. Microlens-like 3D structures were patterned on 300nm wafers using grayscale i-line lithography. These structures were imaged using a SEM tool equipped with a four-quadrant secondary electron (SE) detector, and the resulting data were co-registered with high-resolution Atomic Force Microscopy (AFM) measurements for 3D reference. We analyzed the analytical forward-based SEM model and distinguished between two models, focusing first on Slowko’s model. The updated SEM model denotes as Vynnyk model better describes the SEM signal across the entire microlens surface, including regions oriented towards and opposite the active detector. We developed a method to compute the radius of the microlens directly from the SEM image and refined the height estimation process using this radius calculation. Our 3D reconstruction strategy yielded accurate results for various microlenses with radii ranging from 800nm to 1400nm, achieving a height error below 2%. In conclusion, 3D SEM metrology demonstrates good overall accuracy for microlenses and paves the way towards in-line statistical process control studies, offering a reliable method to compute critical dimensions and improve the precision of height estimation.

This paper presents the challenges and results of implementing an optimization-based scheduling engine in a high-mix 300mm fully automated semiconductor manufacturing facility. Efficient scheduling of lots on photolithography machines is crucial due to their high cost and critical role in production. Optimally managing the transportation, storage and inspection of a large number of masks is essential to ensure this efficiency. Initially deployed in the cleaning and diffusion work center, the optimization engine was adapted for photolithography and is operational since May 2024. This generic engine solves large multi-objective scheduling problems in minutes, considering diverse constraints related to processing and transportation resources, product quality, and global production targets. The successful deployment demonstrates the engine’s potential for full factory scheduling, with ongoing efforts to enhance its genericity, efficiency, and effectiveness.

Modern Integrated Circuits (IC) manufacturing consists of a complex series of process steps and each transition to smaller semiconductor technology nodes has come with a significant increase in the number of steps. Apart from this increased technological complexity, also the cost of semiconductor manufacturing has risen significantly. A high yield is therefore of utmost importance to ensure the overall profitability of the modern IC manufacturing process, meaning that each process step needs to be executed flawlessly, in particular due to accumulative nature of yield loss.

Photolithography is one of the many process steps in IC manufacturing that is executed repeatedly and overlay is one of its most critical parameters. Maintaining good overlay performance is thus key for maximizing yield and guaranteeing the overall profitability of the IC production process. Overlay metrology plays an important role in keeping this good performance in high-volume manufacturing (HVM), and the measurements are used as input for the Advanced Process Control (APC) system as well as for lot dispositioning. Preferably, the amount of metrology is reduced to a bare minimum to reduce cost and decrease fab cycle time, and overlay is typically measured on only a fraction of the wafers. In case metrology reduction is going too far, then there is a risk that bad wafers and/or lots pass, resulting in potential yield loss or even wafer scrap, which will increase the cost again. The challenge is to find the sweet spot for using the available metrology in the most efficient way.

Virtual metrology is a solution that aims to enable metrology coverage for every single wafer, and with that applications like smarter sampling with the goal of using metrology more efficiently. Basically, virtual metrology is the use of algorithms to predict wafer properties like overlay based on previous metrology measurements and/or processing equipment sensor data. In previous work, we developed virtual metrology, or computational overlay, based on a hybrid approach that combines domain knowledge-based physical modeling with machine learning. A good prediction performance was demonstrated on the critical overlay between contact and gate layers that were exposed with chuck dedication. Furthermore, we also showed that computational overlay could be used to reduce the field magnification errors that were observed in the lot-to-lot variation.

In this paper, we build upon our earlier work and extend the applicability of the computational overlay model towards layers that are exposed without chuck dedication, or even on different scanners. We will assess the prediction performance on a few Via layers in the back-end-of-line. Furthermore, as the model is able to predict the overlay for all wafers in the lot, we will demonstrate its capability of detecting an intermittent first wafer effect on one particular lithography cluster that was causing non-optimal quality.

Background: Test patterns are crucial in micro-electronic device patterning because they are fundamental to characterize and model lithography or etch processes.

Problem: Empirical etch models, used to predict wafer pattern shapes, often require extensive pattern characterization to reduce the risk of overfitting with the hope of having good design space coverage. This highlights the critical importance of selecting suitable test patterns. This operation could be facilitated if we had a metric to measure the quality of a test pattern.

Approach: This study utilized post-etch SEM contours from 74 test patterns to train etch models using a neural network, evaluating model performances with the Edge Placement Error (EPE) metric. The idea is to exploit the risk of model instability in neural networks to select and rank the best test pattern candidates based on their model prediction performance. Additionally, it investigates correlations between pattern testing scores and pattern signatures in a multidimensional feature space.

Conclusion: The prediction performance of the machine learning etch model trained from a single pattern is a good metric of the “usefulness” score of the pattern. The scores of the various patterns could be correlated with the pattern feature signatures. Ultimately, this allows selecting or optimizing patterns based on their features only.

In EUV lithography, the leaked light reflected from the border of the image field (image border) can cause unintended pattern transfer on die edge. To prevent such an unexpected exposure, low reflectivity image border, referred to as black border, has been widely adopted. However, the current multilayer etched type black border can have insufficient specifications required for high NA lithography in terms of the reflectivity and border edge quality. In this paper, we investigated stacked absorber type black border, where an additional absorber is stacked on the conventional absorber, as an alternative candidate through optical simulation and preliminary experiment. The simulation shows that stepwise nk change in the additional absorber is an effective design to reduce EUV and DUV reflectivity significantly. In the experiment, we fabricated a test mask blank with the same film structure as the simulation model and measured the reflectivity. It is successfully confirmed that stacked absorber type black border has better optical properties than multilayer etched type.

The multi-beam mask writer MBM-3000, where beam current density increases to 3.6A/cm², the beam count doubles for faster writing speed, and beam size decreases from 16nm to 12nm for higher resolution, has been released since 2023 to support the N2 device technology node. We developed not only the optics with improved writing accuracy for reduction in the Coulomb interaction effects but also a new data path, and moreover introduced a new data format MBF2.1 for efficient handling of curve data. Writing time of MBM-3000 now becomes 10.5 hours when exposure dose is 200 μC/cm². Consequently, the system grows in power compared with previous series including MBM-2000 PLUS.

Development of High-NA EUV scanners is maturing and reached the stage of first exposures. Due to the anamorphic 0.55 NA optics, High-NA EUV masks are designed at (4x,-8x) magnification compared to wafer scale (X,Y). Consequently, while dimensions further shrink in X-direction on mask, they relax in Y-direction, resulting in asymmetric mask patterns and new mask perceptions. In this paper, we present a CD-based characterization for a variety of generic patterns on a state-of-the-art High-NA EUV mask, with emphasis on feature dimensions which are specifically relevant to High-NA EUV lithography. The mask metrology is done using an Advantest E3650 mask CD-SEM at imec, with image capture and metrology settings optimized for EUV masks. Besides providing insight into achievable pitches, we touch upon CD linearity for line-space patterns on mask, local roughness and non-uniformity at different length scales, and include a simulation to discuss the transfer of mask variability to wafer variability for a dense contact hole case. Another important aspect which we highlight in this study, is related to the effect of CD errors on mask. Namely, because of the anamorphic imaging, an X/Y symmetric CD offset on mask will lead to asymmetric CD errors at wafer level which can no longer be absorbed e.g. by choice of exposure dose. To avoid these asymmetries at wafer level, it is important to make sure that the mask is well targeted. The latter, however, also depends on choices in metrology settings, which may be ‘historic defaults’ and based on larger dimensions on DUV masks, yet applied to (High-NA) EUV masks. We therefore appeal to mask vendors for a careful verification of metrology settings applied for measurement on (High-NA) EUV masks.

On product overlay (OPO), with its continually shrinking budget, remains a constraint in increasing device yield. The OPO performance consists of both scanner and process-related contributors. Both groups need to be addressed and optimized to minimize the overlay in order to keep up with Moore’s law. Examples of process-related overlay contributors are wafer distortion due to patterned stressed thin films and/or etch. Masks can never be made identical since they represent different layers of the device. It has been shown that shape measurements of the wafer can help to correct for most process-induced wafer distortions up to the 3^rd order. However, another contributor to overlay challenges is related to photomask flatness. Wafer overlay errors due to non-flatness and thickness variations of a mask need to be minimized. Overlay metrology capability lags the need for improved overlay control, especially for multi-patterning applications. In this paper, we present a new metrology method that generates a very high-resolution shape map of an entire optical photomask optimized for DUV lithography. The technique is measuring the wave front phase change of the reflected light from both the front and backside of a quartz photomask. In this paper we introduce Wave Front Phase Imaging (WFPI), a new method for measuring flatness of an optical photomask that generates a shape map based on local slope. It collects 810 thousand (K) data points on an 86.4mm × 86.4mm area with a spatial resolution of 96μm.

The traceability efforts are important for instance automotive and medical applications where critical components must be validated and monitored during their lifetime. This enables to precisely backtrack individual devices and product groups in case of failure and thereby significantly reduce costs in case of product recalls. The digital lithography system was employed for patterning of the die annotations accomplishing 50×50μm DataMatrix codes by using high resolution RGB resists.

Nano-imprint lithography (NIL) has proven to be a powerful and cost-efficient technology for proto-typing but also the high-volume manufacturing of AR/VR/MR devices and Metalenses. It has the ability to create high-quality replicates of various types of features. These range from small and arbitrarily shaped meta-atoms (e.g. circles, squares, rectangles, diamonds etc) to waveguide gratings used for light transfer in AR/VR/MR devices. However, the latter mentioned gratings are typically not only gratings of vertical patterns. Their application as waveguides requires them to have different, nonvertical shapes such as slanted, blazed or staircase-like pattern. In addition, the duty cycle and the depth of the patterns throughout a grating may vary. All of these patterns need initially to be created on a stamp, the imprint master.

We have successfully demonstrated that these special requirements can be accomplished on nano-imprint masters.

In this paper we will show the variety of Quartz etch technologies that are used for manufacturing of pattern on masters. This ranges from plasma etching, in combination with multi-level e-beam exposure to created staircase like gratings or 3-dimensional patterns (e.g. pyramids). Another technology is ion-beam etching of Quartz in combination with a tilt of the substrate. We will demonstrate how this can be used to create slanted patterns in gratings. This can also be combined with a non-linear variation of etch depth throughout such a grating.

The manufacturing capabilities shown here are a substantial enabler of the technologies required for AR/VR/MR devices, Metalenses and other applications requiring such profiles on an imprint master.

In the European TINKER project, which pushes the development of LiDAR (Light Detection And Ranging) technology, NIL has been explored with the aim of improving manufacturing of the optical structures. More specifically, the main idea is to use NIL to manufacture the waveguide structures of the PIC chips for LiDAR. With this objective, the four partners closely involved in NIL: CEA-Leti, PROFACTOR, EV Group and Inkron, pooled their expertise and demonstrate the high potential of this technique.

This study led to the development of a new imprintable material with a high refractive index. Moreover, specific designs linked to the application and investigating the NIL physicals phenomenon were manufactured. The combination of both, material and design allowed to prove the capability to manufacture waveguide with NIL using the specified index material. The study was completed with optical functional tests. Furthermore, global manufacturing approach was studied and demonstrating the sustainability of NIL manufacturing and its ability to reduce manufacturing time and cost.

With high-NA EUV exposure tools soon to be available for utilization by chip makers, the factors that could limit the useable resolution of these systems are considered, with a view to addressing these potential limitations and thereby enabling patterning close to the theoretical optical resolution limit. Large volumes of solubility-switched resist around sites of photon absorption will limit resolution and lead to large line-edge roughness (LER). If the volumes of chemically converted resist are small, there need to be many such volumes in order to provide continuous paths for development. Hence, the matters of exposure dose and molecular considerations are not fully separable. New resist architectures will be needed to avoid extremely high exposure doses in order to pattern features below 10 nm half-pitch. More energy-efficient EUV light sources will be needed. Computational lithography must account for a multiplicity of issues, necessitating increased automation of mask pattern optimization.

To stabilize the resist profile for subsequent process steps like wet etching or high energy implantation in our 200mm fabrication the so-called UV harden process is used. This UV harden process step, mainly used for MUV resist materials, leads to further cross-linking and curing of the resist material. The aim is to remove most of the solvents still contained in the resist patterns and to destroy the remaining light-sensitive components (photoactive compounds) in order to stabilize the resist profile. At the same time, the adhesion of critical structures to the surface should be improved to provide a better foundation for subsequent patterning or implant processes.

Unfortunately, for the process transfer of our CMOS technologies from 200mm to 300mm fabrication the UV harden process cannot be used due to missing tool availability on the market. Therefore, it is necessary to find an alternative process which is able to substitute the UV harden process with comparable defectivity behavior.

In this paper we will show our evaluations for a detailed understanding of the UV harden process for different DUV and MUV resist materials and process variations. We will present our characterization methods to judge on resist material parameters like etch rate, adhesion or film stress. Additionally, the currently used regular defect density test for our UV harden equipment and processes will be presented.

The microelectronics industry faces constant challenges in improving the quality and performance of electronic circuits, especially when addressing markets with high reliability requirements. One of the main challenges is to improve robustness of our technologies, making a rapid diagnosis of any parametric signature observed.

This paper describes the added value of using a massive e-beam inspection tool combined with CD SEM and contour analysis to accelerate the diagnostic of a process from a variability point of view. Massive CD and contour-based measurement have been used to investigate recurrent but nonsystematic signatures related to Poly Contact shorts risks.

Control plan definition for Critical Dimension (CD) and Overlay (OVL) is set up by performing CD and OVL windowing (modulated wafers in dose for CD and Translation or Scaling for OVL that are sent to yield). The variations are set so that yield failures are reached across the window. These wafers are typically densely measured on reference CD and OVL targets (dedicated metrology structures). The correlation of those measurements to yield leads to in-line specification limits and sampling definition. However, the statistical level of metrology information is not at the same level of yield EWS (Electrical Wafer Sorting) where all dies are measured. Massive e-beam Inspection changes the paradigm by enabling the measurement of every die on the wafer in a reasonable time and better anticipate probability of potential yield excursions.

Poly Contact shorts, is a situation caused by a contact edge getting too close to the gate edge. Process robustness consolidation can be particularly challenging due to the multiple sources of variability in the fabrication process, especially in the patterning process (photolithography and etching process). One of the very first actions in such situations is to perform a process variability breakdown: global (lot to lot, wafer to wafer, intra wafer, intra field) and local (LCDU and PCDU). From previous work it is also known that for critical lithography steps local components happen to be the largest contributors.

In this paper, massive ebeam technology is being used to characterize intra wafer and intra field component for CD and Overlay at die level (with the same spatial resolution as yield EWS map) while contour-based metrology from in-line CDSEM images gives complementary insight on local variability. Combining such “metrology” resources can be called metro-spection approach. This enables more exhaustive variability breakdown and time to decision and qualification is being accelerated. Finally, it will be shown that deploying a new process reducing local pattern CD variability is the most effective solution to increase robustness.

The upcoming introduction of High-NA EUV lithography in chip manufacturing is accompanied by still ongoing activities to mitigate the imaging issues combined with the 3D photomask absorber. Besides suitable exposure and patterning techniques, the mask absorber material has large impact on image contrast and the usable depth of focus. In recent years, 3D mask effects in EUV lithography have widely been investigated, and alternative absorber stacks which enable improved contrast and focus control have been proposed. The study of solutions to the challenges combined with the EUV reflective mask typically is based on rigorous imaging simulations. However, aerial image metrology can be a supplementary way to verify the impact of mask 3D effects on lithography. For this purpose, the AIMS® EUV actinic mask measurement represents a highly precise way to qualify the High-NA mask printing performance under scanner-equivalent optical column conditions.
In this paper, we present an AIMS® EUV study of the impact of mask 3D effects on the through-focus image formation in a three-beam interference regime. Our experiments on a dense vertical 20nm lines and spaces clip using dedicated monopole illumination demonstrate a prominent, focus-dependent line shape deformation for each of the single pole positions. For the center monopole setting, frequency doubling of the aerial image is observed for one particular focus value. To describe the line shapes recorded, we applied an analytical model for three-beam-imaging in the presence of defocus and mask 3D effects. We obtained an excellent agreement between measurements and calculated data that allows us to derive the mutual phase-shifts of the single interference cross-terms involved. We conclude that the aerial image behavior as observed can be traced back to a coupling of the defocus aberration and mask 3D driven effects.

OPC (Optical Proximity Correction) technology has been evolving to assist on the continues improvement of pattern resolution. One approach for further extending lithography resolution is ILT (Inverse Lithography Technology). This technology, based on applying an inverse model to the target design, creates curves from the design layouts. The adoption of ILT is now enabled by the improvement of runtime obtained by enhancements in algorithms and computing power as well as the new generation of mask writers (multibeam) which enables writing complex features in an acceptable time. The last blocking points were the data volume required to store, and the challenge of handling complex structures. If the standard data storage is used, curvilinear shapes are stored as polygons, which produces larger file sizes. The file size issue has been identified and addressed by the industry in recent years. File formats proposing compact ways to represent curves usually propose Implicit Bézier and B-Spline as main curve representations. The recent development of High-NA lithography requires anisotropic scaling of the patterns for writing on mask (4x, 8x). This adds another challenge to the data preparation flow to maintain the benefits of the proposed curve representations. This work assesses the impact of adoption of curvilinear representations, with the spotlight on the needs for High-NA mask data preparation.

Lithography processes are important as they impact following process steps such as etching and deposition. Additionally, to keep up with the feature size reduction race, the number of steps and process complexity are increasing drastically. To maintain performances and produce masks and wafers with correct specifications, yield can be tracked and understood during R&D and production steps through key elements followed by metrology and defectivity analysis.

We propose a metrospection holistic AI-driven software platform composed of metrology and defectivity capabilities. It is oriented to the analysis of any kind of object on all types of images for lithography. Advanced AI powered object and edge detection algorithms help process engineers to quickly track their features of interest, while proposing a large variety of measurements. An analysis can be easily customized to fit customer needs of measurements without technical assistance, which has the advantage of protecting their internal knowledge and intellectual property (IP). In addition, users can quantify defectivity of the process by defining defects or by tracking anomalies. Users provide compliant images for unsupervised and labeled images for supervised methods. These features are available at larger image scale and full wafer view to control processes from the nanoscale to the microscale. With ever growing complexity and quantity of available data, metrospection is becoming essential for process control. Although some software allows users to detect and classify defects, measurements of defects are needed as indicators of their severity, which can be performed by our platform with freedom of measurement’s customization.

Finally, as confidentiality and IP protection are major subjects, our platform allows users to capitalize on their internal development, to easily integrate their own solutions to their version of the product. Our software includes a plugin manager to allow easy customization and updating of the graphical interface to match each user's needs and benefit from the latest advances and drastically increases process control accuracy and throughput.

While the curvilinear mask shapes generated by ILT improve the wafer lithography process window, the efficiency of mask data preparation steps and the MBMW data-path depends on the number of edges used to represent complex curvilinear shapes. Shape simplification methods have been shown to be effective in reducing the number of edges used to represent curvilinear mask data. In this paper, we present the development of an approach to analyze the impact of edge-length variation on curvilinear mask accuracy, which can be used as a practical guidance for edge-based representation of curvilinear shapes for a given mask process.

As advanced semiconductor technologies continuing to evolve, defect detection and classification have experienced increased challenges because the complex process involved with greatly increased transistor density resulting in high defect rates. This makes it more challenging than before for traditional analysis done by human experts prone to error due to long hours of focus required. Software with rules may be used to overcome this, but still faces the issue to construct them, since image quality varies from process to process and layer to layer. In this paper we propose using a machine learning (ML) model, YOLO (You Only Look Once) v8, that will learn complex rules that can generalize to various image qualities and accurately detect defects without human intervention.

The standard tantalum mask gives strong 3D electromagnetic effects, hence, its utilization in foundries to enable further downscaling to the A14 node might reach its limits even with the help of high NA EUV scanners (with 0.55 numerical aperture “NA”). The use of alternative mask absorber materials together with inverse lithography techniques (ILT), such as source mask optimization (SMO), can improve printing of metal logic layers with a target pitch of 20 and 24nm. This is possible due to thinner mask absorber thickness (around 40nm instead of 60nm for Ta-based mask) and due to different EUV optical properties of the mask material causing a different behavior of the light that is reflected by the masks. To better mitigate the light behavior during and after reflection from the mask, materials covering a good portion of the n-k graph (EUV refractive index, n, by EUV extinction coefficient, k) were chosen. The study proposes a comparison between baseline (Ta-based mask) and five new mask absorber candidates, ranging from three materials with lower refractive index and varied extinction coefficient (“low-n” with low-, mid-, and high-k), and two candidates with higher extinction coefficients (“highk” with mid- and high-n).
This paper contains simulation results with the Siemens EDA Calibre tool and demonstrates theoretical proof that alternative mask materials bring significant gain when compared to the tantalum-based mask absorber. Firstly, we optimized the source and aerial image intensity threshold on a set of predefined clips (with SMO techniques). Secondly, we applied ILT techniques to correct for the full chip mask based on a horizontal layout of a metal logic layer on imec’s roadmap. We then compare the tantalum-based mask with the alternative masks using imaging criteria, such as DoF (depth of focus), NILS (Normalized Image log slope), EPE (edge placement error), pattern shifts through focus, process variation band, source telecentricity errors, and MEEF (mask error enhancement factor) on a variety of features in the metal logic clip to maximize the overall process window.