Technitrol, the original designer of MIL-STD-1553 transformers, the original military 1Mb/s LAN, has advanced the state of the art one further notch, introducing a series of transceivers that allow high speed (through 1 Gb/s) data transmission over copper wire instead of fiber optic cable. One such device can be employed to implement the Fiber Channel Interface as defined by hte X3T11 ANSI Fibre Channel Committee using either mini coax, Type 1 shielded twisted pair, twinax or video cable. The technology now exists to upgrade data transmission rates on current physical media to speeds formerly only available with fiber optic cabling. Copper transceiver technology provides a cost effective alternative for dealing with demanding high speed applications such as high speed serial data transfer, high speed disk and tape storage transfer, imaging telemetry, radar, and other avionics applications. Eye diagrams will be presented to show that excellent data transmission at rates of 1 gigabit/sec with low jitter is capable over mini coax at distances to approximately 50 meters, shielded twisted pair and twinax cable to distances of 105 meters, and video cable to distances of 175 meters. Distances are further at lower data rates. As a member of the X3T11 ANSI Fiber Channel Committee, Technitrol has developed a Physical Media (copper wire) Dependant (PMD) transceiver not only compliant with the Fibre Channel Specifications but exceeding the specifications by a factor greater than four. Conceivably, this opens high speed interconnections for today's high data rate requirements to copper cabling systems. Fibre Optic problems need not be dealt with to obtain data transfers for high speed information transfers.

Reliable 100 Mbit/sec data transmission cannot be reliably achieved over two-pair category 3, unshielded twisted pair (UTP) cabling with conventional two-level line signaling schemes. This paper provides an overview of the issues and challenges of designing 100BASE-T2 proposed transceivers. The use of DSP functionality enables an increase in robustness to alien near end crosstalk (NEXT) on adjacent wire pairs. Two use of this functionality for high-speed data transmission over UTP is primarily due to UTP's attenuation and NEXT coupling which increases with frequency and the need to keep radiated emission levels to FCC radiation emissions limit of 30 MHz.

The advances in computing and applications have contributed to migration of networking speeds from the 10 Megabits per second (Mbps) ubiquitous Ethernet networks to 100 Megabits per second (Mbps). In the 100 Mbps fornt-end networking arena, there are several competing standards vying for a reasonable share of the market, the chief amongst them being 100baseTX, 100baseT4 and 100VG-AnyLAN. This paper will provide a brief summary of each of the three competing standards, their applications, and topology.

Fast Ethernet is an order of magnitude faster than regular ethernet, but the rampup, cost reduction and commercialization also appears to be happening ten times quicker. The PCI bus and its performance improvements has also made Fast Ethernet a much more viable solution. The first generation 10/100 Network Interface Cards (NIC), Switches and Repeaters arrived in 1994. Now there are several versions of each available. The PRO/100 series NIC (adapter) began volume shipments in October 1995. The IEEE Standard IEEE-802.3u/D5.3 was passed in record time for technologies of this magnitude. The standard includes 100BaseTX and 100BaseT4. The former requires two pair of Category 5 Unshielded Twisted Pair (UTP) wiring and the latter four pair of Category 3 UTP. 100BaseTX is full duplex capable. 100BaseT4 operates over ordinary telephone wiring cables. The rapid integration into less silicon of all the 10/1000 blocks, and attendant cost reduction is causing even a more viable Fast Ethernet solution, since pricing is converging to that of regular ethernet NICs and Repeaters.

Framework of IP packet delivery with high throughput and small latency using ATM technology in large scaled internets is proposed, while keeping the current subnet model. Router has the mapping functionality between flow-identifier (e.g. in IPv6 header) and VPI/VCI value to forward IP packets cell-by-cell, rather than the conventional packet-by- packet forwarding. By using this cut-thru IP packet forwarding, both resource reservation oriented IP packet flows (i.e. IP packet flow provided by RSVP) and nonresource reservation oriented IP packet flows (i.e. best effort service) experience less packet delivery latency and obtain higher throughput, compared to the conventional hop-by-hop packet forwarding does. In order to perform the cut-thru IP packet forwarding using cell relaying capability in the router, routers exchange the information how the IP packet flows are aggregated into ATM- VCC. This information exchanging is hop-by-hop base, and the cut-thru decision is a matter of every router's local decision. With the hop-by-hop cut-thru IP packet forwarding, soft-state oriented and scalable QoS-ed high speed communication platform can be provided.

This paper describes a system that attaches a color copier to ATM network as a full color image input and output terminal. For still image tranmission, both high quality of the transmitted image and high transmission throughput are required. To achieve this goal, a new image transmission scheme for ATM network is proposed. A design and implementation of a protocol based on the scheme, an image tranmission system and evaluation of its throughput are also discussed. The scheme is based on retransmission with allowing limited number of errors for one block of data. Instead of retransmission, the scheme employs concealment for the cases of small number of errors. Concealment is an error correction method using the redundancy of image data to improve image data quality. The system based on this scheme demonstrated throughput as almost high as the maximum bandwidth of ATM, 156Mbps, with keeping image quality better than 40dB. It is proved that a relaxation of retransmission condition by concealment is effective to achieve high throughput under average ATM netowrk transmission quality. The system can provide 20 pages per minute transmission throughput for 16 pixels/mm resolution full color images.

The available bit rate (ABR) service allows connections to exceed their negotiated data rates during the life of the connections when excess capacity is available in the network. These connections are subject to flow control from the network in the event of network congestion. The ability to dynamically adjust the data rate of the connection can provide improved utilization of the network and be a valuable service to end users. ABR type service is therefore appropriate for the transmission of bursty LAN traffic over a wide area network in a manner that is more efficient and cost effective than allocating bandwdith at the peak cell rate. This paper describes the ABR service and discusses if it is realistic to operate a LAN like service over a wide area using ABR.

The recent availability of asynchronous transfer mode (ATM), fiber channel (FCH), and other data communications technolgies presents an opportunity to dramatically improve the performance of large-scale legacy LAN networks. Integrating these new technologies must be carefully planned and executed. Rapid, complete deployment of these technologies is not feasible because of potential interoperability problems with deployed technologies. Phased migration consistent with standards-approved applications is required. Scaleable coherent interface (SCI) is a new technology that couples systems via their RAM memories. With it, clustered systems can be architected in which elements can be dedicated to specific functions, e.g., handling ATM and FCH. Herein SCI is used to attach a Gateway to an existing node and thereby integrate both ATM and FCH. A prototype network is being developed as a testbed to determine the hardware and software operating systems and applications suitable for such an application.

Over the last 2 to 3 years, ATM has emerged as the strategic technology for the WAN and the LAN environments. This paper will explore ATM's capabilities in the LAN and in particular as a desktop connectivity technology. Because of its bandwidth scalability, ATM can accommodate the various bandwidth needs of desktop client and server platforms from 25 to 155 to 622 Mbps. New and emerging desktop applications like videoconferencing, network- based education, and multimedia applications require the isochronous capabilites of ATM. This paper will focus on application requirements on the desktop and how ATM meets those requirements, along with migration strategies from legacy ALNs to ATM. Costs and timing for desktop migration to ATM are discussed.

The information superhighway is coming closer to reality, because significant progress has been made in developing both private and public netorks in the last several years. ATM, the major technology for transferring multimedia, has been implemented in many backbone applications. However, the key to speed up the deployment of the information superhighway is hinged on the affordability for mass users to access the ATM network from desktop terminals. In addition to cost-effectiveness, the ATM network has to be a high-performance network to carry the increasingly high volumes of information. The ATM SONET 622 Mbps (OC12) optical LAN can provide the bandwidth to serve the high-performance needs; nevertheless, the challenge is to keep the connection cost low. This paper describes an ATM SONET 622 Mbps optical link using the commercially available devices to design a high-performance and low- cost LAN. The design of the LAN using shortwave CD laser tranceivers, ATM SONET OC12 framers, and ATM cell generators/analyzers is analyzed. Furthermore, the test configuration, test methods, and test results are presented to confirm the design analysis and to provide a reliable ATM SONET 622 Mbps LAN design.

Programmable multimedia imaging workstations over a high bandwidth network (ATM) were used to explore the role of multimedia workstations in the telemedicine application. The multimedia workstation is based on the MediaStation 5000 which uses a TMS320C80 Multimedia Video Processor to handle the multimedia bitstreams and image display/processing functions. Although the telemedicine workstation exhibited its high performance and programmability, we found from the experiment that a tighter integration of the multimedia capability with the networking component should be one of the most desired improvements for the telemedicine system to become applicable in routine clinical environments.

This paper presents a fuzzy logic based ATM cell scheduling technique for input buffered nonblocking (ATM) switches. Simulation results indicate that such scheduling significantly reduces the average wait time for high priority cells when compared with single and multiple priority FIFO buffers. Simulations were run on an actual trace of ATM video cells generated by an ATM camera. These ATM video cells were multiplexed with other ATM cells from different sources. The reduction in wait time for high priority traffic is expected to improve the quality-of-service requirements at the communicating ends.

This paper focuses on issues related to the transport of digital video over ATM networks. We begin with a brief motivation focusing on digital coding for video applications. It then relates typical video application expectations for a communication channel with the generic cell based transport ATM provides. The impairments introduced by an ATM network have a significant impact on the presentation quality of video programs it carries. The talk identifies these impairments and discusses in a general nature how their effects can be mitigated by using an ATM adaptation layer. For any particular application, the choice of adaptation scheme will depend heavily on the nature of the application, on the type of video coding used, the availability of standards/implementation agreements, and network cost constraints. The talk concludes by showing how these factors interrelate by providing some real world examples of how MPEG-2 can be transported over ATM based on discussion at the ATM Forum and the ITU.

The main benefit of the throughput improvement that is possible to achieve with link rates of Gb/s in ATM is the exploitation of statistical gain with bursty high peak rate sources. But not only statistical gain justifies the necessity for such advanced technology. High speed ATM switching systems take advantage of the reduction of the number of interface devices (due to multiplexing) and also the number of stages in the ATM switching network, obtaining better figures in the cost/performance ratio. This paper evaluates the network efficiency improvement by using statistical gain and its describes an ATM switch that exploits parallelism and segmentation to perform very high speed ATM switching. With this characteristic it is possible to switch more than 2.5 Gb/s per input/output using CMOS and BiCMOS technologies.

Current high-speed communication networks exhibit gigabit bandwidths. Nevertheless, applications cannot take advantage of these advances due to host interface and machine and system architecture limitations. Today, the main concern is to reduce the protocol overheads imposed on data transfers, minimizing memory copies and implementing off-host communication functions. We propose a novel architecture for real-time distributed systems using a 155Mbit/sATM network. The system is based on an intelligent communication interface board for PCs, which integrates a Transputer, an FPGA and a VRAM to implement flexible high level communication services. These services are multiple copy updates of distributed real-time data on monitoring machines, transfers of audio and video streams coming from several cameras. The main advantages of our architecture over traditional systems include the reduction of the multimedia load imposed on the host processor, the provision of an efficient real-time data service for applications, and the support of existing standard protocols such as TCP/IP for traditional data. The board is being developed and will soon be experimented on a platform with live applications. The interest of this work is reinforced by the fact that integration of a processor and FPGA on a single chip will be available in the near future. Keywords: Asynchronous Transfer Mode (ATM), high speed networks, communication interface architecture, Field Programmable Gate Array (FPGA), Transputer, real-time, distributed applications, multimedia

The recent advances in computer communication technologies have led to the proliferation of new high-speed networks that operate in the Gpbs ranges. The existing implementations of standard communication protocol suites do not properly utilize the performance of these networks. This has intensified the efforts to develop high-performance network subsystems that are capable of utilizing the bandwidth offered by the high-speed networks. In this paper, we introduce a novel approach to implement the buffers of the network subsystems, which is based on memory interleaving concept. Using this approach, the results obtained using simulations show that data copying overhead is reduced, which increases the throughput of the network subsystem. Many of the proposed techniques to improve the performance of the network subsystems are based on parallel processing techniques. However, we show that for bulk data transfer, the interleaved memory network subsystem provides a comparable performance result at a lower cost.

The end-node, comprising host computer and network adaptor, presents one of the key obstacles to true gigabit networking, defined as the ability to deliver a gigabit per second of data to an application. Drawing on the experience of the AURORA gigabit testbed and the OSIRIS network adaptor, this paper focuses on the performance problems created or exacerbated by the architecture of the host computer. We find that workstation architecture is often hostile to the achievement of high networking performance, and propose some approaches to making workstation architecture more 'network friendly'. In addition, since benchmarks are one of the criteria that drive worstation architecture, we propose some ways to create benchmarks that will take networking performance, an increasingly important aspect of host performance, into account.

While many advances have been made in networking, computer architecture, and operating systems, the performance of the combination of these elements as a networked host has been disappointing. Only a fraction of the potential physical layer bandwidth is available to applications running on hosts. This tutorial will focus on the performance of network sybsystems which support asynchronous transfer mode (ATM). From the physical layer through the ATM layer, potential bottlenecks will be identified and characterized to advocate a systems oriented approach to performing future performance optimizations.

As the demand for high-throughput and low-latency communication increases, traditional packet switches with receive-and-forward mode of relaying will have increasing difficulties in meeting users' high traffic volume and high quality-of-service expectation. In this paper we propose a novel packet switch that uses selective switching as its relaying mode, and describe a new optoelectronic LEADER device that supports such an implementation.

We present the design of a rapid single-flux quantum N X N fast-packet TDM switching element that can be used in ATM packet switches. Using simple 3.5-micrometers niobium-trilayer technology, this device would allow the external exchange rate f_e equals 10 Gb/sec per switched channel at the internal clock frequency f₀ equals 40 GHz. The element structure implies that a separate unit provides the address of the destination channel for each packet and resolves packet contentions.

Input queuing has advantages for building ultra-broadband ATM switches with the throughput beyond 100Gb/s because it imposes minimal memory bandwidth requirements. Using a novel multi-tag-queue input module and a novel matrix-unit-cell-scheduling module, our input queue-based ATM switch avoids head-of-line blocking and provides almost 100% utilization. In a 32-port configuration, the switch can deliver an aggregate throughput of 128Gb/s.

An adaptive end-to-end based congestion control scheme to support a class of best effort service known as available bit rate service is being proposed by the ATM forum. In this paper we present the implementation of two variants of this control scheme. In the first scheme known as the explicit forward congestion indication (EFCI) scheme, a single bit is used to convey to the source the state of the network. In the second scheme, known as the explicit rate (ER) scheme, the network informs the sources from time to time, the maximum rate at which they can transmit. We investigate the transient performance of the two controls in the presence of high priority cross traffic. The EFCI mechanism is fundamentally oscillatory in nature and can lead to large cell loss. The ER scheme is very stable, even under extreme loading conditions, with good transient response.

In this apper, a novel approach for introducing effective priorities on high speed DQDB type metropolitan area networks (MANs) is presented. The proposed method can be applied on various bandwidth balancing mechanisms and almost eliminate the effect of low priority traffic on high priority traffic. Its implementation in the case of three bandwidth balancing mechanisms is presented and simulation results are used to investigate the corresponding delay and throughput performance in the presence of multiple priority classes of traffic. A comparison with other, previously proposed, priority mechanisms is also carried out.

This paper describes a new architecture for a scalable multicast ATM switch from a few tens to thousands of input ports. The switch, called Abacus switch, has a nonblocking memoryless switch fabric followed by small switch modules at the output ports; the switch has input and output buffers. Cell replication, cell routing, output contention resolution, and cell addressing are all performed distributedly in the Abacus switch so that it can be scaled up to thousnads input and output ports. A novel algorithm has been proposed to resolve output port contention while achieving input and output ports. A novel algorithm has been proposed to reolve output port contention while achieving input buffers sharing, fairness among the input ports, and multicast call splitting. The channel grouping concept is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput. The Abacus switch has a regular structure and thus has the advantages of: 1) easy expansion, 2) relaxed synchronization for data and clock signals, and 3) building the switch fabric using existing CMOS technology.

Burst-level admission control protocols have been proposed to perform access control to sources that exhibit high burstiness and need not require real-time delivery. To this end, two broad approaches of burst-level admission control can be classified. In the first approach, called tell-and-go, the source transmits its messages immediately in the form of bursts as soon as it receives the message from its application layer. In the second approach, called tell-and- wait, the source first reserves the bandwidth along the virtual circuit using a short request message. The burst is transitted only after the requested bandwidth has been allotted. In this paper, we analyze the performance of both protocols taking into consideration of the fact that the sources are heterogeneous, an important assumption which is absent in all previous analyses. We show that sources which request a higher peak bit rate encounter higher blocking probability, resulting in lower throughput. We then propose a solution to fix this fairness problem so the equitable performance is achieved.

Applications in high speed ATM networks will specify quality of service (QoS) requirements on an end-to-end basis. Typical application QoS metrics are cell loss rate, delay jitter, throughput, and maximum delay. Obviously, the individual network control components will need to provide more stringent quality of service than specified by the applicaiton. In this ppaer, we study (via simulation) how end-to-end QoS parameters provided by the application can be mapped into the QoS numbers used by the individual network control components.

This paper takes a critical look at ATM from the points of view of an infrastructure provider charges with upgrading the campus production network infrastructure. For this task, parameters such as product stability, availability, cost effectiveness and timing is every bit as important as, and arguably more so than the raw capabilities of the competing technologies.