A One-Third Gigaflop Systolic Linear Algebra Processor

P. J. Kuekes; M. S. Schlansker

doi:10.1117/12.944019

28 November 1984 A One-Third Gigaflop Systolic Linear Algebra Processor

P. J. Kuekes, M. S. Schlansker

Proceedings Volume 0495, Real-Time Signal Processing VII; (1984) https://doi.org/10.1117/12.944019
Event: 28th Annual Technical Symposium, 1984, San Diego, United States

Abstract

ESL is building a high performance signal processor for DARPA and the Navy which will use several systolic arrays to do linear algebra operations. These systolic arrays are all constructed from just one type of systolic integrated circuit. This systolic chip performs 32-bit floating point arithmetic at a ten megaflop rate. The chip contains all the registers needed to make it a systolic cell. All the control and registers for doing complex multiplication and addition are included in the chip. The processor contains four types of systolic arrays. The first does matrix multiplication. The second updates the Cholesky factor of a matrix from the corresponding factor of a rank-one modification of the matrix. The third array does forward and backsolves. The fourth does back-solves against many right-hand-sides. These systolic arrays have address generators which allow them to be used on many different sized problems. The detailed control for the machine is created at compile time from high level commands given by the user. Much of the hardware design effort has gone into memories and address generators which support running many different problem sizes on fixed sized arrays.

Citation Download Citation

P. J. Kuekes and M. S. Schlansker "A One-Third Gigaflop Systolic Linear Algebra Processor", Proc. SPIE 0495, Real-Time Signal Processing VII, (28 November 1984); https://doi.org/10.1117/12.944019

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