Novel pattern-centric solution for high performance 3D NAND VIA dishing metrology

Sicong Wang; Jian Mi; Abhishek Vikram; Gao Xu; Guojie Cheng; Liming Zhang; Pan Liu

doi:10.1117/12.2524569

20 March 2019 Novel pattern-centric solution for high performance 3D NAND VIA dishing metrology

Sicong Wang, Jian Mi, Abhishek Vikram, Gao Xu, Guojie Cheng, Liming Zhang, Pan Liu

Author Affiliations +

Proceedings Volume 10962, Design-Process-Technology Co-optimization for Manufacturability XIII; 1096217 (2019) https://doi.org/10.1117/12.2524569
Event: SPIE Advanced Lithography, 2019, San Jose, California, United States

Abstract

The 3D NAND (three-dimensional NAND type) has rapidly become the standard technology for enterprise flash memories, and is also gaining widespread use in other applications. Continued manufacturing process improvements are essential in delivering memory devices with higher I/O performance, higher bit density, and lower cost. Current 3D NAND technology involves process steps that form array and peripheral CMOS (Complementary Metal-Oxide-Semiconductor) regions side-by-side, resulting in waste of silicon real estate and film stress compromises, and limits the paths of making advanced 3D NAND devices. An innovative architecture was invented to overcome these challenges by connecting two wafers electrically through millions of metal VIAs (Vertical Interconnect Access) simultaneously across the whole wafer in one process step [1]. A highly accurate and efficient metrology is required to monitor the VIA interface due to the increased process complexity and precision requirements. With the advanced processing of AFM (Atomic Force Microscopy) images, highly accurate and precise measurements have been achieved. An inline pattern-centric metrology solution that is designed for high volume mass production of high-performance 3D NAND is presented in this paper.

Citation Download Citation

Sicong Wang, Jian Mi, Abhishek Vikram, Gao Xu, Guojie Cheng, Liming Zhang, and Pan Liu "Novel pattern-centric solution for high performance 3D NAND VIA dishing metrology", Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 1096217 (20 March 2019); https://doi.org/10.1117/12.2524569

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