High density integrated isolated deep silicon vias in silicon for 3D-ROIC FPA architectures

Arjun Kar-Roy; Sangki Hong; Yasir Qamar; Robert Patti

doi:10.1117/12.2558890

26 May 2020 High density integrated isolated deep silicon vias in silicon for 3D-ROIC FPA architectures

Arjun Kar-Roy, Sangki Hong, Yasir Qamar, Robert Patti

Proceedings Volume 11407, Infrared Technology and Applications XLVI; 114070E (2020) https://doi.org/10.1117/12.2558890
Event: SPIE Defense + Commercial Sensing, 2020, Online Only

Abstract

Three-dimensional read-out integrated circuit (3D-ROIC) based advanced focal-plane-array (FPA) architectures are driven by the requirements of pixel level analog-to-digital conversion, on-chip digital-signal-processing, high framerates, low read noise, and extended dynamic range. These 3D-ROIC FPAs require hybridization of analog technology ROIC silicon wafers with digital technology ROIC silicon wafers and detectors. Small pitch vias are needed both at the topmost and bottommost surfaces of the analog wafers to facilitate these 3D-ROIC architectures. Although it is easy to build top surface vias, integration of bottom surface vias into the CMOS process flows is uncommon. In this paper, we describe the integration of tungsten-filled isolated deep-silicon-vias (iDSV) extending from metal1 to the handle wafer of the substrate in thick-film SOI based 130nm and 180nm mixed-signal CMOS processes. Major advantages of the iDSV based integration scheme reported here include ease of porting of mixed-signal designs from bulk CMOS to SOI, high density 3D-ROIC interconnect formation with via-middle integration, and an inbuilt buried-oxide etch stop layer for post wafer process thinning for iDSV reveal. These iDSVs have resistances of 2.5Ω/via, breakdown voltages exceeding 50V, and leakage currents to adjacent wells of less than 10fA/via. We report electrical results and process flow of the more complex face-to-back hybrid wafer bonding utilizing the top vias in the daughter wafer and iDSV in the mother wafer with copper direct-bond-interconnect (DBI) hybridization at 4μm pitch. We outline various 3D-ROIC integration architectures for large-format and small pixel FPAs using iDSV and DBI bonding, along with their advantages and disadvantages.

Citation Download Citation

Arjun Kar-Roy, Sangki Hong, Yasir Qamar, and Robert Patti "High density integrated isolated deep silicon vias in silicon for 3D-ROIC FPA architectures", Proc. SPIE 11407, Infrared Technology and Applications XLVI, 114070E (26 May 2020); https://doi.org/10.1117/12.2558890

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KEYWORDS

Semiconducting wafers

Readout integrated circuits

Analog electronics

Oxides

Silicon

Wafer bonding

Copper

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