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Tool Induced Shift (TIS) is a measurement error commonly used to measure the accuracy of metrology tools. TIS manifests in the difference in overlay (OVL) misregistration between measurements of the same target at 0ᴼ and 180ᴼ rotations. This inaccuracy is attributed to tool asymmetries and is commonly caused by lens aberrations, lens alignment, illumination alignment and the tool’s interaction with target asymmetries. TIS impacts tool Total Measurement Uncertainty (TMU) and tool-to-tool matching. In memory chips, particularly 3D NAND, TMU is limited by TIS distribution across wafer, as it depends on process stability and is amplified by high layer topology. Additionally, TIS is influenced by wafer-to-wafer and lot-to-lot process variation. TIS correction by direct measurement per site (TIS-onLink, ToL) incurs a heavy penalty to measurement throughput as it requires measuring each site twice. Alternatively, measuring TIS on a sparse subset of sites, interpolating to other sites (TIS-on-Parent, ToP), induces a lower throughput penalty but is not accurate enough in many cases. In a previous paper we introduced a new methodology to improve overlay measurement with minimum throughput impact - Modeled-TIS (mTIS). This approach uses Machine Learning (ML) algorithms to predict per-site TIS correction on Image-Based Overlay (IBO) measurements. This method gives near ToL TIS correction performance at ToP throughput penalty, or better, depending on the use case. In this paper, we describe some of the algorithmic adaptations we made to the original algorithm to work in a high-volume manufacturing (HVM) environment and present results of an HVM use case on 3D NAND production lots.
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