Scatterometry of nanowire/nanosheet FETs for advanced technology nodes

Madhulika Korde; Subhadeep Kal; Cheryl Alix; Nick Keller; G. Andrew Antonelli; Aelan Mosden; Alain C. Diebold

doi:10.1117/12.2584751

22 February 2021 Scatterometry of nanowire/nanosheet FETs for advanced technology nodes

Madhulika Korde, Subhadeep Kal, Cheryl Alix, Nick Keller, G. Andrew Antonelli, Aelan Mosden, Alain C. Diebold

Proceedings Volume 11611, Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV; 116111S (2021) https://doi.org/10.1117/12.2584751
Event: SPIE Advanced Lithography, 2021, Online Only

Abstract

Here, we report the measurement of the dielectric spacer etch process for nanowire and nanosheet FET processes. A previously described Nanowire Test Structure (NWTS) was used for this study.[1, 2, 3] This structure has alternating Si/Si_1-xGe_x/…/Si multilayers. Subsequent to the selective etching of the Si_1-xGe_x layers (cavity etch), a silicon nitride (SiN) dielectric layer was deposited on the NWTS. Here we report on the use of Mueller Matrix Spectroscopic Ellipsometry based Scatterometry (MMSE) to measure the thickness of the SiN dielectric layer after deposition and after trim etch steps. Four different amounts of trim etch were characterized.

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Citation Download Citation

Madhulika Korde, Subhadeep Kal, Cheryl Alix, Nick Keller, G. Andrew Antonelli, Aelan Mosden, and Alain C. Diebold "Scatterometry of nanowire/nanosheet FETs for advanced technology nodes", Proc. SPIE 11611, Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV, 116111S (22 February 2021); https://doi.org/10.1117/12.2584751

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