Investigating the effect of variation and parasitics on the latest next generation architectures

Joseph Ervin

doi:10.1117/12.2587750

22 February 2021 Investigating the effect of variation and parasitics on the latest next generation architectures

Joseph Ervin

Proceedings Volume 11614, Design-Process-Technology Co-optimization XV; 1161412 (2021) https://doi.org/10.1117/12.2587750
Event: SPIE Advanced Lithography, 2021, Online Only

Abstract

Design Technology Co-Optimization (DTCO) has become a critical toolset in navigating the tradeoffs between design targets and manufacturing constraints. Some methodologies for understanding these tradeoffs include 3D design rule validation, patterning optimization, design vs. manufacturing yield studies and fully-integrated process and electrical performance modeling. In this presentation, we will discuss how fully-integrated “virtual” DTCO can be used to predict and ameliorate potential manufacturing and design issues prior to wafer-based testing. We will provide examples of how virtual DTCO can be used to predict optimal integration and patterning schemes, highlight areas of potential device failure, predict yield limiters, and gain a better understanding of how process variation can impact device performance. Our discussion will focus on process variation and parasitic impacts that are critical at 5nm and beyond, and we will share valuable insights learned from DTCO studies of next generation architectures.

Conference Presentation

Citation Download Citation

Joseph Ervin "Investigating the effect of variation and parasitics on the latest next generation architectures", Proc. SPIE 11614, Design-Process-Technology Co-optimization XV, 1161412 (22 February 2021); https://doi.org/10.1117/12.2587750

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