EPE variability comparison study of multiple patterning options for restricted 2D structures in advanced logic nodes

Arup Saha; Brett Schroeder; Tsann-Bim Chiou; Fung Suong Ou

doi:10.1117/12.2584615

22 February 2021 EPE variability comparison study of multiple patterning options for restricted 2D structures in advanced logic nodes

Arup Saha, Brett Schroeder, Tsann-Bim Chiou, Fung Suong Ou

Author Affiliations +

Proceedings Volume 11615, Advanced Etch Technology and Process Integration for Nanopatterning X; 116150M (2021) https://doi.org/10.1117/12.2584615
Event: SPIE Advanced Lithography, 2021, Online Only

Abstract

In this paper, we compare EPE (Edge Placement Error) variability among various multiple patterning techniques such as SADP and SALELE using simple restricted 2D design of “grating” (30 nm pitch) and “cut” (15 nm tip-to-tip) EUV patterns. The lithography variability contribution to CD uniformity is carried out through Tachyon® SMO generated contours by considering dose, focus, flare, mask variations. SEMulator3D is used to run a large Monte Carlo simulation to capture the following sources of variation: resist “contours” (from Tachyon®), spacer thickness, overlay for each of the lithography exposures and etch. We developed a methodology to combine lithography and other fab processes, particularly etch and deposition, involved in multi-patterning processes for EPE characterization of given layout. For the layout considered in this study, we find that Spacer Assisted Litho-Etch-Litho-Etch (SALELE) is more adaptable to multi-patterning process for extension to 2D layouts compared to Self Aligned Double Patterning (SADP). Per this study, the differences in the two multi-patterning approaches are primarily attributed to better litho performance (lower global CDU and larger process margin) and lower process variability on most process metrics.

Conference Presentation

Citation Download Citation

Arup Saha, Brett Schroeder, Tsann-Bim Chiou, and Fung Suong Ou "EPE variability comparison study of multiple patterning options for restricted 2D structures in advanced logic nodes", Proc. SPIE 11615, Advanced Etch Technology and Process Integration for Nanopatterning X, 116150M (22 February 2021); https://doi.org/10.1117/12.2584615

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