Innovative techniques in comparator designs

Renjun Huang; Ke Tian; Ji Xia

doi:10.1117/12.2640501

15 July 2022 Innovative techniques in comparator designs

Renjun Huang, Ke Tian, Ji Xia

Proceedings Volume 12258, International Conference on Neural Networks, Information, and Communication Engineering (NNICE 2022); 122582T (2022) https://doi.org/10.1117/12.2640501
Event: International Conference on Neural Networks, Information, and Communication Engineering (NNICE 2022), 2022, Qingdao, China

Abstract

This paper studies five innovative designs of comparators proposed these years. The dynamic bias comparator ensures that the pre-amplifier output nodes are only partially discharged to reduce the energy consumption. The comparator with a floating inverter amplifier (FIA)-based pre-amplifier realizes the stability of input common-mode voltage and reduces influence of the process corner, moreover, thereby greatly boosting gm/ID and reduce noise, offset and delay. The edgepursuit comparator (EPC) has unique ability to adapt energy cost automatically, it can provide a new idea for the design of comparator. Triple-latch feedforward dynamic comparator (TLFF) with minimized stacking achieved < 70-ps delay in a wide common-mode (VCM) and power supply (VDD) range, and with the increase of input voltage, its delay advantage is more obvious. Low-Power High-Speed Dynamic Comparator in the evaluation phase, the latch reduces energy consumption and delay by delaying activation and using small cross-coupled transistors

Citation Download Citation

Renjun Huang, Ke Tian, and Ji Xia "Innovative techniques in comparator designs", Proc. SPIE 12258, International Conference on Neural Networks, Information, and Communication Engineering (NNICE 2022), 122582T (15 July 2022); https://doi.org/10.1117/12.2640501

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KEYWORDS

Energy efficiency

Transistors

Chromium

Curium

Amplifiers

Capacitors

Feedback loops

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