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Acting as one of the three critical indicators to evaluate the performance of lithography scanners, overlay has been a vital factor which seriously affects the electric property, life span and reliability of integrated circuits (IC). With continuous developments of technology nodes and applications of resolution enhancement technologies (RET), current resolution of the scanners has shrunk to 7 nm and beyond, proposing more stringent requirements for measuring, monitoring and correcting the overlay error. To ensure that the overlay budget fully met by the scanner, advanced optical technologies and holistic alignment approaches have been gradually applied to the alignment system of the scanner, revealing that an integrated methodology in which multiple technologies are adopted proved to be valid and effective in reducing the overlay error in present technology nodes. In this article, the exact concept of overlay error is provided, and on this basis different methods to describe the overlay error are comprehensively analyzed from the perspectives of classifications, sources, quality control and correcting models. Then the systematic relationship between alignment and overlay is illustrated. Recent improvements in the alignment system are also the key points here to systematically reduce the overlay error, including the optimization of the alignment optical path, mark types and design procedures, as well as the application of optimal color weighting (OCW), wafer alignment model mapping (WAMM) and sampling scheme optimization (SSO) algorithms. Based on the combined application and iteration of these technologies, it is believed that the on-product overlay (OPO) can be further compressed to support the continuous tightening of the overlay budget in the industry of IC.
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