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DRAM cell scaling down to the 14 nm design rule (D/R) has already been productized by major DRAM players such as Samsung, Micron, and SK Hynix. They’re developing n+1 (12~13 nm) and n+2 (11 nm or beyond) so-called D1b (D1β), D1c (D1γ), and D1d (D1δ) or even D0a generation now, which means DRAM cell D/R might be able to further scale down to single digit nm with EUVL adoption for DRAM cell/core patterning. The cell design scaling down is getting slower due to many scaling issues including patterning, leakage, and sensing margin. Major DRAM players have applied EUVL masks (such as SS_BLP/H_SC2) on DRAM and will expand it for the next generation. Current 6F2 cell architecture with 1T+1C will be moving over to 4F2 or 3D DRAM in an 8~9 nm D/R DRAM generation due to scaling limitations, which will be D0b or D0c. Although they change to 3D DRAM with a little relaxed CDs, EUVL will be a must for the performance and yield improvement (defects) in DRAM core areas such as very dense WLD and SA patterns just near the cell array. HKMG DRAM process has been adopted on Graphic DRAM and advanced DDR5 DRAM products by Samsung and Micron, although etching and high-k engineering are different for each. Major NAND manufacturers are still in the race to increase the number of vertical 3D NAND gates, they all have already introduced their own 176L/232L/238L 3D NAND devices. Samsung V-NAND, KIOXIA/WDC BiCS, Intel FG CuA, Micron CTF CuA, SK Hynix 4D PUC, and YMTC Xtacking 3D NAND products are the mainstream for SSD and mobile storage applications. Many innovative processes and designs have been adopted, however, lots of challenges are still there to overcome. Although lithography burdens were reduced by changing 2D to 3D, instead, UHAR etching/cleaning/filling-related developments are ongoing. Micron already exited XPoint memory, and Intel is winding it down as well. For SCM applications, fast NAND and some Emerging Memory (EM) devices such as Z-NAND, XL-FLASH, and STT-MRAM will cover the market needs in the future. Due to the difficulties of the EM materials etching, they’re currently limited to embedded and low-density applications only. We’ll discuss current and future challenges on DRAM, 3D NAND, and Emerging memory including process, design, and materials.
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