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Variability control has been a key enabler for achieving continuing technology shrinks in both logic as well as DRAM. With ever-tightening requirements, simple one-dimensional metrology and control aspects, i.e. separate variability control for CD and overlay, are no longer adequate [1]. To improve on this approach, simultaneous control of more than one parameter has been discussed to minimize the parametric yield impact. One such example is to improve edge placement error (EPE), a metric where overlay and CD metrology are combined [1]. In this work, we will revisit the EPE concept from the perspective of using established methodologies used in yield modeling. Rather than starting with a litho-centric approach, we cast the problem as a parametric yield loss mechanism driven by patterning parameters. In contrast to the widely disseminated EPE budget that originates from a patterning process-centric view, we introduce a modified analysis framework. The development of the approach discussed in this work starts with well-known yield engineering approaches rooted in defectivity modeling/statistics. It then proceeds towards quantifying and thus allowing a statistically sound quantification and thus prioritization of patterning (i.e. litho or post etch) improvements based on their impact on the yield loss Pareto. In doing so, the new formalism sheds light on what aspects of the EPE distribution most prominently affects yield loss. It also reveals that the ratio of potentially failing instances with a die and the max number of fails tolerable before the die fails plays a role in formulating any kind of budget approach. When putting our concepts to the test we discovered that there is yet another significant contributor affecting the acceptable variation range. We find that the “rigid structure approach”, an inherent assumption in any budget breakdown, and feature-to-feature interactions drive a significant reduction of the available processing tolerances. We attribute this mechanism to the 3D aspects of the patterning process and present a model that can handle the interactions. Finally, we discuss our approach to addressing the fact that process variability happens on length scales that cover several orders of magnitude. We developed a physical budget breakdown that attempts to optimize the tradeoff between sample size and the ability to capture variability over this wide range of length scales. We will postpone our discussion on other sampling-related topics. The question of how one obtains all required metrology data on one wafer in a manufacturing environment will be addressed in a future publication.
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