Paper
10 October 2023 An FPGA routing algorithm to improve efficiency and quality
Rui Zhu, Chengjun Li
Author Affiliations +
Proceedings Volume 12799, Third International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023); 1279908 (2023) https://doi.org/10.1117/12.3005873
Event: 3rd International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023), 2023, Kuala Lumpur, Malaysia
Abstract
With the continuous increase in the size and integration of Field Programmable Gate Arrays (FPGAs), the running time of FPGA Electronic Design Automation (EDA) software has become longer and longer, gradually constraining the healthy development of FPGAs. Among the various stages of the FPGA EDA process, the routing stage is one of the most time-consuming, and the routing results directly affect the performance of the implemented circuit. To address this issue, this paper proposes a high-efficiency and high-quality FPGA routing algorithm, EQRouter. EQRouter improves the performance of the routing algorithm by enhancing the maze routing algorithm and the rip-up and re-route strategy in the Versatile Place and Route (VPR) routing algorithm. Experimental results show that, compared to the VPR 7 router, EQRouter achieves a 24.6%, 14%, and 12% reduction in routing time, critical path delay, and circuit bus length, respectively, on 10 MCNC benchmark circuits.
(2023) Published by SPIE. Downloading of the abstract is permitted for personal use only.
Rui Zhu and Chengjun Li "An FPGA routing algorithm to improve efficiency and quality", Proc. SPIE 12799, Third International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023), 1279908 (10 October 2023); https://doi.org/10.1117/12.3005873
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KEYWORDS
Field programmable gate arrays

Algorithm development

Electronic design automation

Detection and tracking algorithms

Industry

Software development

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