High-speed array controller: design of a 64-channel detector controller

Tim Hardy; Erning Zhao; Greg Burley

doi:10.1117/12.3020846

27 August 2024 High-speed array controller: design of a 64-channel detector controller

Tim Hardy, Erning Zhao, Greg Burley

Proceedings Volume 13103, X-Ray, Optical, and Infrared Detectors for Astronomy XI; 1310322 (2024) https://doi.org/10.1117/12.3020846
Event: SPIE Astronomical Telescopes + Instrumentation, 2024, Yokohama, Japan

Conference Poster

Abstract

We present the design and initial tests of the HIgh-speed Array Controller (HIAC) developed at NRC to operate high frame rate multi-channel imaging detectors. The development of HIAC was prompted by the need for a controller to operate the SaphiraQM infrared APD array, which has 64 output channels running at up to 10Mpx/s each. No available controller had this capability. The controller is based around a Xilinx Zynq system-on-chip (SoC) module with multiple processor cores and programmable logic, which provides plenty of computing resources and real-time sequencing capability, as well as sufficient high-speed transceivers for handling the data communication. The highly flexible nature of the Zynq device allows the system to be reprogrammed to operate many types of detectors. Two compact prototype systems have been built from a Zynq development board and some custom analog circuit boards. One is designed to operate the SaphiraQM and the other to operate a large format CMOS imager with a digital interface (CIS120). Initial tests demonstrate the system's ability to handle high-speed data acquisition and processing effectively, achieving synchronization and accurate signal capture across all channels.

Citation Download Citation

Tim Hardy, Erning Zhao, and Greg Burley "High-speed array controller: design of a 64-channel detector controller", Proc. SPIE 13103, X-Ray, Optical, and Infrared Detectors for Astronomy XI, 1310322 (27 August 2024); https://doi.org/10.1117/12.3020846

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