Trap resistance triggers SCR with low capacitance

Zhiwen Zeng; Yang Wang; Hongke Tao; Wei Liu; Shuang Li

doi:10.1117/12.3039790

28 August 2024 Trap resistance triggers SCR with low capacitance

Zhiwen Zeng, Yang Wang, Hongke Tao, Wei Liu, Shuang Li

Proceedings Volume 13251, Ninth International Conference on Electromechanical Control Technology and Transportation (ICECTT 2024); 132510F (2024) https://doi.org/10.1117/12.3039790
Event: 9th International Conference on Electromechanical Control Technology and Transportation (ICECTT 2024), 2024, Guilin, China

Abstract

In this paper, an ESD protection device for high-speed I/O interface circuits is proposed, and an SCR protection device utilizing trap resistance triggering and reduced parasitic capacitance is designed and investigated, and verified in a 0.18 μm CMOS process. The design has a low overshoot voltage under ESD stress, a high failure current, a sufficiently low parasitic capacitance, and a low leakage current, and is therefore suitable for low-voltage ESD protection for high-speed circuits in CMOS processes.

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Zhiwen Zeng, Yang Wang, Hongke Tao, Wei Liu, and Shuang Li "Trap resistance triggers SCR with low capacitance", Proc. SPIE 13251, Ninth International Conference on Electromechanical Control Technology and Transportation (ICECTT 2024), 132510F (28 August 2024); https://doi.org/10.1117/12.3039790

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