Understanding metrology of polysilicon gates through reflectance measurements and simulation

Karim H. Tadros; Andrew R. Neureuther; Roberto Guerrieri

doi:10.1117/12.44433

1 July 1991 Understanding metrology of polysilicon gates through reflectance measurements and simulation

Karim H. Tadros, Andrew R. Neureuther, Roberto Guerrieri

Author Affiliations +

Proceedings Volume 1464, Integrated Circuit Metrology, Inspection, and Process Control V; (1991) https://doi.org/10.1117/12.44433
Event: Microlithography, 1991, San Jose, CA, United States

Abstract

A massively parallel computer simulation algorithm is used to investigate electromagnetic scattering and optical imaging issues related to linewidth measurement of polysilicon gate structures. The algorithm simulates scattering of normally incident, TE polarized illumination by inhomogeneous, nonplanar, 2-dimensional topography. The thickness and extinction coefficient of the polysilicon layer (nominally 450 nm thick) are determined from reflectivity versus wavelength data gathered using a Nanometrics Nanospec/DUV microspectrophotometer. These parameters are used as part of the input for the simulator which computes the diffraction efficiencies of the polysilicon gate structure. A spectral component-weighting technique was applied for estimating optical microscope images based on the diffraction efficiencies from normally incident illumination. Simulated image profiles of isolated edges and 1.2 micrometers lines are then compared with images obtained using an NBS-type optical microscope at VLSI Standards, Inc. and show good agreement. The dramatic effects of an 8 nm variation in polysilicon thickness on the electric field distribution within the gate, on reflectivity and on the image profile are illustrated. Also, the effect of focus position is shown by comparing measured and simulated image profiles at different focus offsets.

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Karim H. Tadros, Andrew R. Neureuther, and Roberto Guerrieri "Understanding metrology of polysilicon gates through reflectance measurements and simulation", Proc. SPIE 1464, Integrated Circuit Metrology, Inspection, and Process Control V, (1 July 1991); https://doi.org/10.1117/12.44433

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