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1 May 1994 Design for a high precision, high accuracy SEM stage for metrology and review
James J. Jackman, F. Span, H. Tappel, R. v. d. van Vucht
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Proceedings Volume 2196, Integrated Circuit Metrology, Inspection, and Process Control VIII; (1994) https://doi.org/10.1117/12.174123
Event: SPIE's 1994 Symposium on Microlithography, 1994, San Jose, CA, United States
Abstract
Metrology of critical dimensions in an automated fashion requires that stage precision is such that interwafer repeatability be better than approximately 1 micrometers . This limits the need for pattern recognition. Review applications require that the stage can `blind'-navigate to a specific location as a result of an electrical test or defect detection. The extensive use of modal analysis in both the pre-design and test phases has shown the value of this technique, the measured and the pre-calculated resonant (eigen) frequencies being within 5% of each other. We implemented a fully automated mapping procedure that uses pattern recognition techniques to map the encoder errors and global errors relative to a reference wafer. A correction program has been built to provide absolute accuracy results typically of 1.5 micrometers 3 (sigma) with an offset less than 0.2 micrometers over 25 mm (die size) and 2 micrometers 3 (sigma) with a 0.5 micrometers offset for the whole wafer.
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James J. Jackman, F. Span, H. Tappel, and R. v. d. van Vucht "Design for a high precision, high accuracy SEM stage for metrology and review", Proc. SPIE 2196, Integrated Circuit Metrology, Inspection, and Process Control VIII, (1 May 1994); https://doi.org/10.1117/12.174123
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KEYWORDS
Metrology
Scanning electron microscopy
Pattern recognition
Semiconducting wafers
Computer programming
Defect detection
Modal analysis
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