Paper
19 November 2001 Improved heuristics for optimal parallel multiplier synthesis
Troy Townsend, Michael Liebelt
Author Affiliations +
Proceedings Volume 4593, Design, Characterization, and Packaging for MEMS and Microelectronics II; (2001) https://doi.org/10.1117/12.448852
Event: International Symposium on Microelectronics and MEMS, 2001, Adelaide, Australia
Abstract
Parallel multipliers are of increasing importance for VLSI design, largely driven by the significant increase in demand for computer graphics and digital signal processing. The fastest (and, when pipelined, most area-efficient) multiplier class is partial product reduction tree (PPRT) based multipliers. The previous best known heuristic for PPRT design (published by Stelling et al.) is capable of producing the fastest possible circuits but suffers an infeasible computational burden. This paper introduces some results which significantly reduce the search space of this heuristic. Consequently, the speed of netlist generation is increased, and the circuits generated retain optimal performance. In addition, larger optimal multipliers may be synthesised due to the easing of the computational burden.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Troy Townsend and Michael Liebelt "Improved heuristics for optimal parallel multiplier synthesis", Proc. SPIE 4593, Design, Characterization, and Packaging for MEMS and Microelectronics II, (19 November 2001); https://doi.org/10.1117/12.448852
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KEYWORDS
Chemical elements

Algorithm development

3D modeling

Computer graphics

Digital signal processing

Time division multiplexing

Very large scale integration

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