Scheduling components for multigigabit network SoCs

Theofanis Orphanoudakis; George Kornaros; Ioannis Papaefstathiou; Helen-Catherine Leligou; Stylianos Perissakis; Nicholas Zervos

doi:10.1117/12.498488

21 April 2003 Scheduling components for multigigabit network SoCs

Theofanis Orphanoudakis, George Kornaros, Ioannis Papaefstathiou, Helen-Catherine Leligou, Stylianos Perissakis, Nicholas Zervos

Author Affiliations +

Proceedings Volume 5117, VLSI Circuits and Systems; (2003) https://doi.org/10.1117/12.498488
Event: Microtechnologies for the New Millennium 2003, 2003, Maspalomas, Gran Canaria, Canary Islands, Spain

Abstract

To meet the demand for higher performance, flexibility, and economy in today's state-of-the-art networks, great emphasis is placed on unconventional hardware architectures of network processors. This paper analyzes the problem of processor internal resource and traffic management and proposes a programmable scheduler architecture implemented in a novel protocol processor that deals with the above problems in an integrated way. We briefly outline the architecture of the protocol processor and we support that the innovative scheduling scheme integrated in PRO3 is, in general, crucial for network Systems-on-Chip since it makes it feasible to use scheduler's architecture are discussed that lead to efficient integration of the component to different network processor architectures at a similar cost. Its beneficial features are easy hardware implementation, low memory bandwidth requirements and high flexibility so as to support multiple service disciplines in a programmable way, thousands of flows and even perform different scheduling tasks.

Citation Download Citation

Theofanis Orphanoudakis, George Kornaros, Ioannis Papaefstathiou, Helen-Catherine Leligou, Stylianos Perissakis, and Nicholas Zervos "Scheduling components for multigigabit network SoCs", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); https://doi.org/10.1117/12.498488

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