Simulation of void formation in interconnect lines

Alireza Sheikholeslami; Clemens Heitzinger; Helmut Puchner; Fuad Badrieh; Siegfried Selberherr

doi:10.1117/12.498783

21 April 2003 Simulation of void formation in interconnect lines

Alireza Sheikholeslami, Clemens Heitzinger, Helmut Puchner, Fuad Badrieh, Siegfried Selberherr

Proceedings Volume 5117, VLSI Circuits and Systems; (2003) https://doi.org/10.1117/12.498783
Event: Microtechnologies for the New Millennium 2003, 2003, Maspalomas, Gran Canaria, Canary Islands, Spain

Abstract

The predictive simulation of the formation of voids in interconnect lines is important for improving capacitance and timing in current memory cells. The cells considered are used in wireless applications such as cell phones, pagers, radios, handheld games, and GPS systems. In backend processes for memory cells, ILD (interlayer dielectric) materials and processes result in void formation during gap fill. This approach lowers the overall k-value of a given metal layer and is economically advantageous. The effect of the voids on the overall capacitive load is tremendous. In order to simulate the shape and positions of the voids and thus the overall capacitance, the topography simulator ELSA (Enhanced Level Set Applications) has been developed which consists of three modules, a level set module, a radiosity module, and a surface reaction module. The deposition process considered is deposition of silicon nitride. Test structures of interconnect lines of memory cells were fabricated and several SEM images thereof were used to validate the corresponding simulations.

Citation Download Citation

Alireza Sheikholeslami, Clemens Heitzinger, Helmut Puchner, Fuad Badrieh, and Siegfried Selberherr "Simulation of void formation in interconnect lines", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); https://doi.org/10.1117/12.498783

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