Edge printability: techniques used to evaluate and improve extreme wafer edge printability

Bill Roberts; Cort Demmert; Igor Jekauc; Jason Prettyboy Tiffany

doi:10.1117/12.535323

24 May 2004 Edge printability: techniques used to evaluate and improve extreme wafer edge printability

Bill Roberts, Cort Demmert, Igor Jekauc, Jason Prettyboy Tiffany

Author Affiliations +

Proceedings Volume 5375, Metrology, Inspection, and Process Control for Microlithography XVIII; (2004) https://doi.org/10.1117/12.535323
Event: Microlithography 2004, 2004, Santa Clara, California, United States

Abstract

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

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Bill Roberts, Cort Demmert, Igor Jekauc, and Jason Prettyboy Tiffany "Edge printability: techniques used to evaluate and improve extreme wafer edge printability", Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); https://doi.org/10.1117/12.535323

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KEYWORDS

Semiconducting wafers

Yield improvement

Etching

Sensors

Lithography

Wafer-level optics

Overlay metrology

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