System to improve RET-OPC production by dynamic design coverage using sign-off litho simulator

Mark C. Simmons; Jean-Marie Brunet; Seung-Weon Paek; Y. K. Kim

doi:10.1117/12.771821

4 March 2008 System to improve RET-OPC production by dynamic design coverage using sign-off litho simulator

Mark C. Simmons, Jean-Marie Brunet, Seung-Weon Paek, Y. K. Kim

Proceedings Volume 6925, Design for Manufacturability through Design-Process Integration II; 69250X (2008) https://doi.org/10.1117/12.771821
Event: SPIE Advanced Lithography, 2008, San Jose, California, United States

Abstract

The advanced process technologies have well known yield loss due to the degradation of pattern fidelity. The process to compensate for this problem is advanced resolution enhancement techniques (RET) and optical proximity correction (OPC). By design, the creation of RET/OPC recipes and the calibration of process models are done very early in the process development cycle with data that are not made of real designs since they are not yet available, but made of test structures that represent different sizes, distances and topologies. The process of improving the RET/OPC recipes and models is long and tedious, it is usually a key contributor to quick production ramp-up. It is very coverage limited by design. The authors will present a proposed system that, by design, is dynamic, and allows the RET/OPC production system to reach maturity faster through a detailed collection of hotspots identified at the design stage. The goal is to reduce the lapse of time required to get mature production RET/OPC recipes and models.

Citation Download Citation

Mark C. Simmons, Jean-Marie Brunet, Seung-Weon Paek, and Y. K. Kim "System to improve RET-OPC production by dynamic design coverage using sign-off litho simulator", Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69250X (4 March 2008); https://doi.org/10.1117/12.771821

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KEYWORDS

Optical proximity correction

Product engineering

Process modeling

Computer aided design

Resolution enhancement technologies

Semiconducting wafers

Data modeling

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