Paper
13 May 2008 Low-cost ladar imagers
S. Vasile, J. Lipson
Author Affiliations +
Abstract
We have developed low-cost LADAR imagers using photon-counting Geiger avalanche photodiode (GPD) arrays, signal amplification and conditioning interface with integrated active quenching circuits (AQCs) and readout integrated circuit (ROIC) arrays for time to digital conversion (TDC) implemented in FPGA. Our goal is to develop a compact, low-cost LADAR receiver that could be operated with room temperature Si-GPD arrays and cooled InGaAs GPD arrays. We report on architecture selection criteria, integration issues of the GPD, AQC and TDC, gating and programmable features for flexible and low-cost re-configuration, as well as on timing resolution, precision and accuracy of our latest LADAR designs.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
S. Vasile and J. Lipson "Low-cost ladar imagers", Proc. SPIE 6950, Laser Radar Technology and Applications XIII, 69500P (13 May 2008); https://doi.org/10.1117/12.781586
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CITATIONS
Cited by 5 scholarly publications and 1 patent.
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KEYWORDS
LIDAR

Readout integrated circuits

Field programmable gate arrays

Receivers

Sensors

Imaging systems

Indium gallium arsenide

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