High order wafer alignment for 20nm node logic process

Bumhwan Jeon; Shyam Pal; Sohan Mehta; Subramany Lokesh; Yun Tao Jiang; Chen Li; Mark Yelverton; Yayi Wei

doi:10.1117/12.2010709

18 April 2013 High order wafer alignment for 20nm node logic process

Bumhwan Jeon, Shyam Pal, Sohan Mehta, Subramany Lokesh, Yun Tao Jiang, Chen Li, Mark Yelverton, Yayi Wei

Author Affiliations +

Proceedings Volume 8681, Metrology, Inspection, and Process Control for Microlithography XXVII; 868110 (2013) https://doi.org/10.1117/12.2010709
Event: SPIE Advanced Lithography, 2013, San Jose, California, United States

Abstract

Advanced thermal annealing processes used for transistor enhancing for the state of the art process nodes induce wafer grid deformations. RTA (Rapid Thermal Anneal) and LSA (Laser Scanning Anneal) processes are a few examples. High Order Wafer Alignment (HOWA) method is an effective wafer alignment strategy for wafers with distorted grid signature especially when wafer-to-wafer grid distortion variations are also present. However, usage of HOWA in high volume production environment requires 1) careful initial determination of optimum polynomial order and alignment sampling to be implemented, and 2) matched tool monitoring and controlling strategies and infrastructures to avoid potential HOWA induced drawbacks (i.e. alignment walking).

Citation Download Citation

Bumhwan Jeon, Shyam Pal, Sohan Mehta, Subramany Lokesh, Yun Tao Jiang, Chen Li, Mark Yelverton, and Yayi Wei "High order wafer alignment for 20nm node logic process", Proc. SPIE 8681, Metrology, Inspection, and Process Control for Microlithography XXVII, 868110 (18 April 2013); https://doi.org/10.1117/12.2010709

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