Patterning and etch challenges for future DRAM and other high aspect ratio memory device fabrication

N. R. Rueger; A. McGinnis; F. Good; A. J. Schrinsky; M. Kiehlbauch

doi:10.1117/12.2015286

29 March 2013 Patterning and etch challenges for future DRAM and other high aspect ratio memory device fabrication

N. R. Rueger, A. McGinnis, F. Good, A. J. Schrinsky, M. Kiehlbauch

Proceedings Volume 8685, Advanced Etch Technology for Nanopatterning II; 86850E (2013) https://doi.org/10.1117/12.2015286
Event: SPIE Advanced Lithography, 2013, San Jose, California, United States

Abstract

Current challenges are outlined for masking materials that enable future high aspect ratio (AR> 25) etch requirements. At such high aspect ratios, and 20nm to 30nm feature sizes, ion energy flux loss due to sidewall collisions, feature gap necking, polymerization, and feature charging in deep via-like structures has driven etch process conditions into very high bias voltage regimes. At these ion energies (keV), lateral removal of mask material due to faceting is the dominating mask erosion mechanisms. Using carbon as our baseline hard mask film, we present here normalized performance comparisons of 13 alternative films. We demonstrate that feature CD changes that correlate to lateral mask loss on the test structure also correlate to lateral mask loss on a real patterned structure and that we can therefore use these test structures as a tool for hard mask film evaluation without having the capability to pattern the hard mask under investigation. We propose that such test structures can be a valuable tool for film development as they relate to hard mask applications in dry etch patterning, and should be used in future development efforts rather than the more classical methods of blanket etch rate analysis. Such test structures can also be used to study film etch properties in general and we show that they are capable of capturing ARDE and sputter redeposition phenomena. Correlations between surface loss/addition as a function of sidewall position are presented and results of in-practice applications are shown. Key issues for future hard mask film implementation are discussed from the perspective of photo patterning, dry etching, wet etching, and integration.

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N. R. Rueger, A. McGinnis, F. Good, A. J. Schrinsky, and M. Kiehlbauch "Patterning and etch challenges for future DRAM and other high aspect ratio memory device fabrication", Proc. SPIE 8685, Advanced Etch Technology for Nanopatterning II, 86850E (29 March 2013); https://doi.org/10.1117/12.2015286

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KEYWORDS

Etching

Data centers

Ions

Optical lithography

Carbon

Critical dimension metrology

Sputter deposition

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