Fabrication of silicon-embedded low resistance high-aspect ratio planar copper microcoils

Zishan Ali Syed Mohammed; Poenar Daniel Puiu; Sheel Aditya

doi:10.1117/1.JMM.17.1.014501

9 January 2018 Fabrication of silicon-embedded low resistance high-aspect ratio planar copper microcoils

Zishan Ali Syed Mohammed, Poenar Daniel Puiu, Sheel Aditya

Author Affiliations +

Funded by: Ministry of Education—Singapore (MOE)

Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol. 17, Issue 1, 014501 (January 2018). https://doi.org/10.1117/1.JMM.17.1.014501

Abstract

Low resistance is an important requirement for microcoils which act as a signal receiver to ensure low thermal noise during signal detection. High-aspect ratio (HAR) planar microcoils entrenched in blind silicon trenches have features that make them more attractive than their traditional counterparts employing electroplating through a patterned thick polymer or achieved through silicon vias. However, challenges met in fabrication of such coils have not been discussed in detail until now. This paper reports the realization of such HAR microcoils embedded in Si blind trenches, fabricated with a single lithography step by first etching blind trenches in the silicon substrate with an aspect ratio of almost 3∶1 and then filling them up using copper electroplating. The electroplating was followed by chemical wet etching as a faster way of removing excess copper than traditional chemical mechanical polishing. Electrical resistance was further reduced by annealing the microcoils. The process steps and challenges faced in the realization of such structures are reported here followed by their electrical characterization. The obtained electrical resistances are then compared with those of other similar microcoils embedded in blind vias.

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Zishan Ali Syed Mohammed, Poenar Daniel Puiu, and Sheel Aditya "Fabrication of silicon-embedded low resistance high-aspect ratio planar copper microcoils," Journal of Micro/Nanolithography, MEMS, and MOEMS 17(1), 014501 (9 January 2018). https://doi.org/10.1117/1.JMM.17.1.014501

Received: 10 August 2017; Accepted: 18 December 2017; Published: 9 January 2018

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KEYWORDS

Copper

Silicon

Resistance

Electroplating

Etching

Diffractive optical elements

Semiconducting wafers

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