KEYWORDS: Inspection, Semiconducting wafers, Wafer inspection, Defect inspection, Signal processing, Optical proximity correction, System on a chip, Lithography, Semiconductors, Logic
As electronic users demand smaller form factor of devices that can pack more functionality, Semiconductor industry has
been marching towards smaller design rules. With the advancement in newer design nodes such as 32nm and beyond,
additional challenges are being faced by the Fabs developing the process technologies. These challenges are often
difficult to solve using traditional approaches and therefore novel techniques must be implemented to address the
challenges accordingly. In the area of wafer inspection, the traditional approach of simply using wafer level data alone
is no longer sufficient. Some specific challenges regarding systematic defects that the Fabs are facing today are
discussed in this paper along with several approaches that can help meet the challenges. These new approaches can help
to take the wafer inspection to the next level in order to detect and identify key yield deterrents that limit reaching yield
entitlement in a timely manner.
As design rules continue to shrink beyond the lithography wavelength, pattern printability becomes a significant
challenge in fabrication for 45nm and beyond. Model-based OPC and DRC checkers have been deployed using
metrology data such as CD to fine-tune the model, and to predict and identify potential structures that may fail in a
manufacturing environment. For advanced technology nodes with tighter process windows, it is increasingly important
to validate the models with empirical data from both product and FEM wafers instead of relying solely on traditional
metrology and simulations. Furthermore, feeding the information back to designers can significantly reduce the
development efforts.
Defect inspections performed in R&D may often result in 100k to 1M defect counts on a
single wafer. Such defect data combine systematic and random defects that may be yield
limiting or just nuisance defects. It is difficult to identify systematic defects from defect
wafer map by traditional defect classification where random sample of 50 to 100 defects
are reviewed on review SEM. Missing important systematic defect types by traditional
sampling technique can be very costly in device introduction. Being able to efficiently
sample defects for SEM review is not only challenging, but can result in a Pareto that lacks
in usefulness for R& D and for yield improvement.
To mitigate the issue and to reduce yield improvement cycle in advanced technology, a
novel method has been proposed. Instead of using random sampling method, we have
applied a pattern search engine to correlate defect of interest (DOI) to its pattern
background. Based on the approach we have identified an important defect type, STI cave
defect, to be the major defect type on defect Pareto. For the defect type, stack die map
was generated that indicated a distinctive signature. The result was compared against
design layout to confirm that the defects were occurring at certain locations of design layout.
Afterwards the defect types were reviewed using SEM and in-line FIB for further
confirmation. We have found the cause of this void defect type to be poor gap-fill in
deposition step. Based on the novel technique, we were able to filter out a systematic
defect type quickly and efficiently from wafer map that consist of random and systematic
defects.
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