Large-array EMCCD requires a complex and large number of drive signals. To solve this problem, this paper designs a large-array EMCCD drive circuit system, which uses large-scale integrated circuit FPGA to generate EMCCD’s timing signal, multiplication signal and DC bias signal, using Verilog language for hardware description, and using the integrated AD chip to sample the analog output signal of EMCCD. Then use the idea of "ping-pong" operation to control DDR3 to complete the splicing of multi-channel digital images. Finally, based on the KAE-02150 EMCCD chip produced by ON Semi, the design of a large-area internal line transfer EMCCD camera was realized.
Electron-Multiplying Charge Coupled Device (EMCCD) is an all-solid-state low-light imaging device in the true sense, and it is an emerging device. Its high sensitivity, all-weather imaging and other technical characteristics have very important applications in military, astronomy and other fields. Based on the working principle of EMCCD, this paper analyzes the principle of noise generation and the countermeasures of the imaging system, and proposes an efficient EMCCD imaging system design method. We choose the Kintex-7 series FPGA of Xilinx Company as the core processing unit, and designed related drive circuits, acquisition circuits, storage circuits and communication circuits. The performance of the module is verified by driving CCD201 of E2V Company, and the signal-to-noise ratio of the module is tested and analyzed. The results show that the EMCCD imaging system in this paper has good low-noise performance
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