The utilization of SRAM-based FPGAs in the implementation of embedded systems is in continuous growth. The flexibility that these devices offer in terms of hardware re-programming can be also a critical point to take into account when designing fault tolerant systems. As configuration values are stored in volatile memory, any event that affects this configuration memory can lead to undesirable changes in the circuits and as a consequence, erroneous outcomes can be obtained. This paper presents an approach to add fault tolerance in an aerospace application implemented in a commercial-off-the shelf FPGA (Virtex-5). By using this device, the partial reconfiguration facility can be exploited. This feature allows us to get more flexibility in hardware management at run-time also as a mean to correct specific parts of the system when faults are detected. Results regarding influence in area by using different approaches are presented.
KEYWORDS: Field programmable gate arrays, Logic, System on a chip, Signal processing, Remote sensing, Satellites, Computer architecture, Data processing, Prototyping, Aerospace engineering
Systems on Chip (SoC) are present in a wide range of applications. This diversity in addition with the quantity of critical
variables involved in their design process becomes it as a great challenging topic. FPGAs have consolidated as a
preferred device to develop and prototype SoCs, and consequently Partial Reconfiguration (PR) has gained importance
in this approach. Through PR it is possible to have a section of the FPGA operating, while other section is disabled and
partially reconfigured to provide new functionality. In this way hardware resources can be time-multiplexed and
therefore it is possible to reduce size, cost and power. In this case we focus on the implementation of a SoC, in an
FPGA-based board, with one of its peripherals being a reconfigurable partition (RP). Inside this RP different hardware
modules defined as reconfigurable modules (RM) can be configured. Thus, the system is suitable to have different
hardware configurations depending on the application needs and FPGA limitations, while the rest of the system
continues working. To this end a MicroBlaze soft-core processor is used in the system design and a Virtex-5 FPGA
board is utilized to its implementations. A remote sensing application is used to explore the capabilities of this approach.
Identifying the section(s) of the application suitable of being time-shared it is possible to define the RMs to place inside
the RP. Different configurations were carried out and measurements of area were taken. Preliminary results of the
performance-area utilisation are presented to validate the improvement in flexibility and resource usage.
KEYWORDS: Signal processing, Global Positioning System, Clocks, Parallel computing, Remote sensing, Data storage, Computer architecture, Satellites, Receivers, Data processing
The increasing campaigns of GNSS-R scenario have put great pressure on high performance post-processing
design into the space level instrumentation. Due to large scale of information acquisition and the intensive
computation of cross-correlation waveform (CC-WAV), the overhead between the processing time and the storage
of amount of data prior to downlink issues has lead us to get the solution of real-time parallel processing design on
board. In this paper, we focus on the interaction of the chip level multiprocessing architecture and applications,
which show that the unbalanced workload of the transmission and processing can be compensated on the novel
architecture, Heterogeneous Transmission and Parallel Computing Platform (HTPCP). The intention of HTPCP
is to get a solution for the bus congestion and memory allocation issues. The pros and cons of SMP and HTPCP
are discussed, and the simulation results prove that HTPCP can highly improve the throughput of the GOLD-RTR
system.
This paper presents a top-down design methodology for a behavioral modeling System, based on smart sensors for
aerospace structures monitoring, implemented on a MATLAB/Simulink environment. The modeled acquisition platform
in this aeronautic health monitoring systems (AHMS) is built using the following specific sensors: humidity, pressure,
temperature, stress and acceleration. For this application it has been implemented frequency acquisition techniques
ensuring optimum noise immunity, particularly: a signal acquisition technique based on voltage to frequency converter,
capacitance to frequency and frequency to code converters (VtoF-cC, CtoF-cC). The Simulink model presents a high
accuracy level in signal acquisition and conditioning compared to the electrical system simulation behavior.
The remote sensing techniques have put great pressure on real-time waveform post-processing design. Due to the
intensive computation and multi-channel waveform integration, the overhead between the processing time and the
storage of amount of data prior to downlink issues has lead us to get the solution of task-level parallelism. With the
development of IC design and innovation of architecture, embedded system can range from a single microprocessor to a
complex multi-processor and even including the embedded operating system (OS) on a chip. Therefore symmetric
multiprocessing (SMP) with embedded OS offers an attractive way to expose coarse-grained parallelism application.
In this paper we demonstrate a new modeling approach. In order to simplify the system; a workload model is derived
from a remote sensing application, which represents the workload characteristic and time degrading factors. The
intention is to leverage the task-level parallelism load is evenly to each processor in SMP, with the OS level testing to
speculate the bottleneck in hardware level. This parallel workload model which maps to a 6-LEON3 SMP architecture,
attains a 2.7x mean speedup over a single-LEON3 baseline; with 3-LEON3 attains a 2.23x mean speedup; with 2-
LEON3 attains a 1.78x mean speedup over a single-LEON3 baseline. Due to the involved sharing resources and
scheduling of multiple CPUs, the system will have a degrading in processing speed. With this lag we could infer the
hardware pipeline efficiency. And afford on the processor-set subsystem and memory subsystem analysis reveal the
affects on the system throughput.
KEYWORDS: Microelectromechanical systems, Sensors, Analog electronics, Smart sensors, Gyroscopes, Linear filtering, Signal processing, Digital electronics, Systems modeling, Device simulation
The extended use of microelectromechanical systems (MEMS) in the development of new microinstrumentation for aerospatial applications, which combine extreme sensitivity, accuracy and compactness, introduced the need to simplify their design process in order to reduce the design time and cost. The recent apparition of analogue and mixed signal extensions of hardware descriptions languages (VHDL-AMS, Verilog-AMS and SystemC-AMS) permits to co-simulate the HDL (VHDL and Verilog) design models for the digital signal processing and communication circuitry with behavioral models for the non digital parts (analog and mixed signal processing, RF circuitry and MEMS components). Since the beginning of the microinstrumentation design process the modeling and simulation could help to define better the specifications and in the architecture selection and in the SoC design process in a more realistic environment. We will present our experience in the application of these languages in the design of microinstruments by using behavioral modeling of MEMS.
KEYWORDS: Smart sensors, Sensors, Microelectromechanical systems, Linear filtering, Systems modeling, Analog electronics, Integrated circuit design, Oscillators, Signal processing, Mathematical modeling
The objective of this work is to develop a modeling of a complete smart sensor to be used in a distributed architecture, with the new modeling language, VHDL-AMS. This smart sensor is composed by a sensor or actuator, for example we have used a piezoresistive accelerometer, its signal conditioning module, with both analogue and digital elements, and a bus driver that allows communication with the instrument control device and other sensors. In that way, it is also possible to introduce these microsensors in a distributed architecture that permits communication between microinstruments. This example of modeling through VHDL-AMS shows how this language allows a multitechnological description of a microsystem, including not only electrical signals, but also thermical, kinematic, fluidic, etc. signals. This language also permits to describe systems in different levels of complexity and abstraction, giving the possibility of covering several models from a physical model until a behavioral model, which can be used to obtain a design methodology for MEMS, analogous to the existent design methodology for integrated circuits. The combination of smart sensors models at behavioral level with the microinstrument control circuit models is a first step in the development of a complete design methodology.
KEYWORDS: Sensors, Telecommunications, Transducers, Iterated function systems, Microelectromechanical systems, Data communications, Microsystems, Data modeling, Control systems, Smart sensors
A microelectromechanical system (MEMS) merges integrated sensors, microactuators, and low-power electronics. These systems normally have a local sensor communication bus managed by a master node. The purpose of this work is to implement a communication interface that permit connect the integrated MEMS local bus (through the master node) with on a high level microinstrument communication bus. The basic philosophy of this development has been to create an IP model with VHDL for the bus module interface. This interface can be added easily to a microsystem and from of point of view of microinstrument design methodology, MEMS based in this interface module could be easily plugged with the other microsystems on microinstrument architecture. The IP developed is based on the concept of Interface File System (IFS) that contains all relevant information of the microsystem. The use of the IFS in integrated microsystems design permits to insulate its particular characteristics from the whole of microinstrument. Also, this IFS has associated a communication model that allows different views of the system, such as, real-time or command service view, configuration and diagnostic service view. Implementation experiences presented in this paper show that the IFS reduces the complexity of microinstrument applications and make easy the MEMS reuse in other microinstruments. The communication module based on IFS was successfully tested between microsystems based on local sensor bus namely IBIS (Interconnection Bus for Integrated Sensors) and a generic real time microinstrument bus.
Our main objective in this work has been to develop a comunication system applicable between sensors and actuators and the data processing circuitry inside the microsystem in order to develop a flexible and modular architecture. This communication system is based on the use of a dedicated sensor bus composed by only two wires (a bidirectional data line and a clock line for sincronization). The basic philosophy of this development has been to create an IP model with VHDL for the bus driver that can be added to the sensor or the actuator to create an smart device that could be easily plugged with the other componets of the microsystem architecture. This methodology can be applied to a high integrated microsystem based on an extensively use of microelectronics technologies (ASICs, SoCs & MCMs). The reduced number of wires is an extraordinary advatage because produce a minimal interconnection between all the components and as a consequence the size of the microinstrument becomes smaller. The second aspect that we have considered in this development has been to reach a communication protocol that permits to built-up a very simple but robust bus driver interface that minimize the circuit overhead. This interconnection system has been applied to biomedical and aerospatial microsystems applications.
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