The significant features of a series of stabilization experiments conducted at the National Renewable Energy Laboratory (NREL) between May 2009 and the present are reported. These experiments evaluated a procedure to stabilize the measured performance of thin-film polycrystalline cadmium telluride (CdTe) and copper indium gallium diselenide (CIGS) thin-film photovoltaic (PV) modules. The current-voltage (I-V) characteristics of CdTe and CIGS thin-film PV devices and modules exhibit transitory changes in electrical performance after thermal exposure in the dark and/or bias and light exposures. We present the results of our case studies of module performance versus exposure: light soaked at 65°C; exposed in the dark under forward bias at 65°C; and, finally, longer-term outdoor exposure. We find that stabilization can be achieved to varying degrees using either light-soaking or dark-bias methods and that the existing IEC 61646 light-soaking interval may be appropriate for CdTe and CIGS modules with one caveat: it is likely that at least three exposure intervals are required for stabilization.
KEYWORDS: Capacitance, Sodium, Data mining, Remote sensing, Solar cells, Solar energy, Reliability, Thin film devices, Algorithm development, Data modeling
A new data mining algorithm was developed to identify the strongest correlations between capacitance data (measured
between -1.5 V and +0.49 V) and first- and second-level performance metrics (efficiency [η%], open-circuit voltage
[VOC], short-circuit current density [JSC], and fill-factor [FF]) during the stress testing of voltage-stabilized CdS/CdTe
devices. When considering only correlations between first- and second-level metrics, 96.5% of the observed variation in
η% was attributed to FF. The overall decrease in VOC after 1,000 hours of open-circuit, light-soak stress at 60°C was
about -1.5%. As determined by our algorithm, the most consistent correlation existing between FF and third-level
metric capacitance data at all stages during stress testing was between FF and the apparent CdTe acceptor density (Na)
calculated at a voltage of +0.49 V during forward voltage scans. Since the contribution of back-contact capacitance to
total capacitance increases with increasing positive voltage, this result suggests that FF degradation is associated with
decreases in Na near the CdTe/back contact interface. Also of interest, it appears that capacitance data at these higher
voltages appears to more accurately fit the one-sided abrupt junction model.
KEYWORDS: Copper indium gallium selenide, Thin films, Photovoltaics, Thin film solar cells, Solar cells, Thin film devices, Copper, Renewable energy, Solar energy, Cadmium
The significant features of a series of stabilization experiments conducted at the National Renewable Energy Laboratory
(NREL) between May 2009 and the present are reported. These experiments evaluated a procedure to stabilize the
measured performance of thin-film polycrystalline cadmium telluride (CdTe) and copper indium gallium diselenide
(CIGS) thin-film photovoltaic (PV) modules. The current-voltage (I-V) characteristics of CdTe and CIGS thin-film PV
devices and modules exhibit transitory changes in electrical performance after thermal exposure in the dark and/or bias
and light exposures. We present the results of our case studies of module performance versus exposure: light-soaked at
65°C; exposed in the dark under forward bias at 65°C; and, finally, longer-term outdoor exposure. We find that
stabilization can be achieved to varying degrees using either light-soaking or dark bias methods and that the existing IEC
61646 light-soaking interval may be appropriate for CdTe and CIGS modules with one caveat: it is likely that at least
three exposure intervals are required for stabilization.
Transient or hysteresis effects in polycrystalline thin film CdS/CdTe cells are a function of pre-measurement
voltage bias and whether Cu is introduced as an intentional dopant during back contact fabrication. When Cu is added,
the current-density (J) vs. voltage (V) measurements performed in a reverse-to-forward voltage direction will yield
higher open-circuit voltage (Voc), up to 10 mV, and smaller short-circuit current density (Jsc), by up to 2 mA/cm2,
relative to scanning voltage in a forward-to-reverse direction. The variation at the maximum power point, Pmax, is
however small. The resulting variation in FF can be as large as 3%. When Cu is not added, hysteresis in both Voc and
Jsc is negligible however Pmax hysteresis is considerably greater. This behavior corroborates observed changes in
depletion width, Wd, derived from capacitance (C) vs voltage (V) scans. Measured values of Wd are always smaller in
reverse-to-forward voltage scans, and conversely, larger in the forward-to-reverse voltage direction. Transient ion drift
(TID) measurements performed on Cu-containing cells do not show ionic behavior suggesting that capacitance transients
are more likely due to electronic capture-emission processes. J-V curve simulation using Pspice shows that increased
transient capacitance during light-soak stress at 100 °C correlates with increased space-charge recombination. Voltagedependent
collection however was not observed to increase with stress in these cells.
CdS/CdTe photovoltaic solar cells were made on two different transparent conducting oxide (TCO) structures in order to
identify differences in fabrication, performance, and reliability. In one set of cells, chemical vapor deposition (CVD)
was used to deposit a bi-layer TCO on Corning 7059 borosilicate glass consisting of a F-doped, conductive tin-oxide
(cSnO2) layer capped by an insulating (undoped), buffer (iSnO2) layer. In the other set, a more advanced bi-layer
structure consisting of sputtered cadmium stannate (Cd2SnO4; CTO) as the conducting layer and zinc stannate (Zn2SnO4;
ZTO) as the buffer layer was used. CTO/ZTO substrates yielded higher performance devices however performance
uniformity was worse due to possible strain effects associated with TCO layer fabrication. Cells using the SnO2-based
structure were only slightly lower in performance, but exhibited considerably greater performance uniformity. When
subjected to accelerated lifetime testing (ALT) at 85 - 100 °C under 1-sun illumination and open-circuit bias, more
degradation was observed in CdTe cells deposited on the CTO/ZTO substrates. Considerable C-V hysteresis, defined as
the depletion width difference between reverse and forward direction scans, was observed in all Cu-doped CdTe cells.
These same effects can also be observed in thin-film modules. Hysteresis was observed to increase with increasing
stress and degradation. The mechanism for hysteresis is discussed in terms of both an ionic-drift model and one
involving majority carrier emission in the space-charge region (SCR). The increased generation of hysteresis observed
in CdTe cells deposited on CTO/ZTO substrates suggests potential decomposition of these latter oxides when subjected
to stress testing.
Polycrystalline photovoltaic (PV) modules containing cadmium telluride (CdTe) or copper indium gallium diselenide
(CIGS) thin film materials can exhibit substantial transient or metastable current-voltage (I-V) characteristics depending
on prior exposure history. Transient I-V phenomena confound the accurate determination of module performance, their
reliability, and their measured temperature coefficients, which can introduce error in energy ratings models or servicelifetime
predictions. Indeed, for either of these two technologies, a unique performance metric may be illusory without
first specifying recent exposure or stateeven at standard test conditions. The current standard preconditioning
procedure for thin-film PV modules was designed for amorphous silicon (a-Si), and is likely inadequate for CdTe and
CIGS. For a-Si, the Staebler-Wronski effect is known to result from defects, created via breaking of weak silicon bonds
or light-activated trapping at the device junction, occurring rapidly upon light-exposure. For CdTe and CIGS devices,
there is less agreement on the causes of metastable behavior. The data suggests that either deep-trapping of charge
carriers, or the migration and/or electronic activation of copper may be responsible. Because these are quite disparate
mechanisms, we suspect that there may be a more practical preconditioning procedure that can be employed prior to
accurate performance testing for CdTe and CIGS modules. We devise a test plan to examine and compare the effects of
light soaking versus forward-biased dark exposure at elevated temperatures, as parallel strategies to determine a feasible
standard protocol for preconditioning and stabilizing these polycrystalline PV technologies, and report on the results of
our tests.
Solar cell module reliability is inextricably linked to cell-level reliability. This is particularly so with thin-film
technologies. In CdTe, reliability issues historically associate with back contact stability and the use of Cu as an
extrinsic dopant. Using a simple approach by which identical cells are heated under open-circuit bias and 1-sun
illumination, degradation activation energies of 0.63 and 2.94 eV in laboratory-scale CdS/CdTe devices were identified
in the accelerated stress temperature range of 60 to 120 °C. At lower stress temperatures, cell performance changes were
linearly correlated with changes in both fill factor (FF) and short-circuit current (Jsc). At higher stress temperatures,
changes in efficiency were correlated with changes in FF and open-circuit voltage (Voc). The measured activation
energy of 0.63 is associated with Cu-diffusion. During the early stage of stress testing, which may provide additional
back contact annealing, improvements in FF were due to Cu-diffusion. Decreased performance observed at longer stress
times (decreased FF and Voc), according to a two-diode Pspice model, were due to both increased space-charge
recombination (near the junction) and decreased recombination in the bulk. Kirkendall void formation (S-outdiffusion) at
the CdS/CdTe interface is given as responsible for the 2.9 eV degradation mechanism.
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