Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.
Overlay control based on DI metrology of optical targets has been the primary basis for run-to-run process control for many years. In previous work we described a scenario where optical overlay metrology is performed on metrology targets on a high frequency basis including every lot (or most lots) at DI. SEM based FI metrology is performed ondevice in-die as-etched on an infrequent basis. Hybrid control schemes of this type have been in use for many process nodes. What is new is the relative size of the NZO as compared to the overlay spec, and the need to find more comprehensive solutions to characterize and control the size and variability of NZO at the 1x nm node: sampling, modeling, temporal frequency and control aspects, as well as trade-offs between SEM throughput and accuracy.
Shrinking technology nodes and smaller process margins require improved photolithography overlay
control. Generally, overlay measurement results are modeled with Cartesian polynomial functions for both intra-field
and inter-field models and the model coefficients are sent to an advanced process control (APC)
system operating in an XY Cartesian basis. Dampened overlay corrections, typically via
exponentially or linearly weighted moving average in time, are then retrieved from the APC system
to apply on the scanner in XY Cartesian form for subsequent lot exposure. The goal of the above
method is to process lots with corrections that target the least possible overlay misregistration
in steady state as well as in change point situations. In this study, we model overlay errors on
product using Zernike polynomials with same fitting capability as the process of reference (POR) to
represent the wafer-level terms, and use the standard Cartesian polynomials to represent the
field-level terms. APC calculations for wafer-level correction are performed in Zernike basis while
field-level calculations use standard XY Cartesian basis. Finally, weighted wafer-level correction
terms are converted to XY Cartesian space in order to be applied on the scanner, along with
field-level corrections, for future wafer exposures. Since Zernike polynomials have the property of
being orthogonal in the unit disk we are able to reduce the amount of collinearity between terms
and improve overlay stability. Our real time Zernike modeling and feedback evaluation was performed
on a 20-lot dataset in a high volume manufacturing (HVM) environment. The measured on-product
results were compared to POR and showed a 7% reduction in overlay variation including a 22% terms
variation. This led to an on-product raw overlay Mean + 3Sigma X&Y improvement of
5% and resulted in 0.1% yield improvement.
Advancing technology nodes with smaller process margins require improved photolithography overlay control. Overlay control at develop inspection (DI) based on optical metrology targets is well established in semiconductor manufacturing. Advances in target design and metrology technology have enabled significant improvements in overlay precision and accuracy. One approach to represent in-die on-device as-etched overlay is to measure at final inspection (FI) with a scanning electron microscope (SEM). Disadvantages to this approach include inability to rework, limited layer coverage due to lack of transparency, and higher cost of ownership (CoO). A hybrid approach is investigated in this report whereby infrequent DI/FI bias is characterized and the results are used to compensate the frequent DI overlay results. The bias characterization is done on an infrequent basis, either based on time or triggered from change points. On a per-device and per-layer basis, the optical target overlay at DI is compared with SEM on-device overlay at FI. The bias characterization results are validated and tracked for use in compensating the DI APC controller. Results of the DI/FI bias characterization and sources of variation are presented, as well as the impact on the DI correctables feeding the APC system. Implementation details in a high volume manufacturing (HVM) wafer fab will be reviewed. Finally future directions of the investigation will be discussed.
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