KEYWORDS: Sensors, Field emission displays, High dynamic range image sensors, X-ray detectors, CMOS sensors, X-rays, Photons, Neon, Modulation transfer functions, High dynamic range imaging
Compared to published amorphous-silicon (TFT) based X-ray detectors, crystalline silicon CMOS-based active-pixel detectors exploit the benefits of low noise, high speed, on-chip integration and featuring offered by CMOS technology. This presentation focuses on the specific advantage of high image quality at very low dose levels. The measurement of very low dose performance parameters like Detective Quantum Efficiency (DQE) and Noise Equivalent Dose (NED) is a challenge by itself. Second-order effects like defect pixel behavior, temporal and quantization noise effects, dose measurement accuracy and limitation of the x-ray source settings will influence the measurements at very low dose conditions. Using an analytical model to predict the low dose behavior of a detector from parameters extracted from shot-noise limited dose levels is presented. These models can also provide input for a simulation environment for optimizing the performance of future detectors. In this paper, models for predicting NED and the DQE at very low dose are compared to measurements on different CMOS detectors. Their validity for different sensor and optical stack combinations as well as for different x-ray beam conditions was validated.
Qiaole Zhao, Ben Schelen, Raymond Schouten, Rein van den Oever, Rene Leenen, Harry van Kuijk, Inge Peters, Frank Polderdijk, Jan Bosiers, Marcel Raspe, Kees Jalink, Jan Geert Sander de Jong, Bert van Geest, Karel Stoop, Ian Young
We have built an all-solid-state camera that is directly modulated at the pixel level for frequency-domain fluorescence lifetime imaging microscopy (FLIM) measurements. This novel camera eliminates the need for an image intensifier through the use of an application-specific charge coupled device design in a frequency-domain FLIM system. The first stage of evaluation for the camera has been carried out. Camera characteristics such as noise distribution, dark current influence, camera gain, sampling density, sensitivity, linearity of photometric response, and optical transfer function have been studied through experiments. We are able to do lifetime measurement using our modulated, electron-multiplied fluorescence lifetime imaging microscope (MEM-FLIM) camera for various objects, e.g., fluorescein solution, fixed green fluorescent protein (GFP) cells, and GFP-actin stained live cells. A detailed comparison of a conventional microchannel plate (MCP)-based FLIM system and the MEM-FLIM system is presented. The MEM-FLIM camera shows higher resolution and a better image quality. The MEM-FLIM camera provides a new opportunity for performing frequency-domain FLIM.
Qiaole Zhao, Ian Ted Young, Ben Schelen, Raymond Schouten, Rein van den Oever, René Leenen, Harry van Kuijk, Inge Peters, Frank Polderdijk, Jan Bosiers, Kees Jalink, Sander de Jong, Bert van Geest, Karel Stoop
We have built an all-solid-state camera which is directly modulated at the pixel level for frequency
domain fluorescence lifetime imaging microscopy (FLIM) measurement. This novel camera eliminates
the need for an image intensifier through the use of an application-specific CCD design,
which is being used in a frequency domain FLIM system. The first stage of evaluation for the
camera has been carried out. Camera characteristics such as noise distribution, dark current influence,
camera gain, sampling density, sensitivity, linearity of photometric response, and contrast
modulation transfer function have been studied through experiments. We are able to do lifetime
measurement using MEM-FLIM cameras for various objects, e.g. fluorescence plastic test slides,
fluorescein solution, fixed GFP cells, and GFP - Actin stained live cells.
We developed an ultrahigh-speed color video camera that operates at 1,000,000 fps (frames per second) and had capacity to store 288 frame memories.
In 2005, we developed an ultrahigh-speed, high-sensitivity portable color camera with a 300,000-pixel single CCD (ISIS-V4: In-situ Storage Image Sensor, Version 4). Its ultrahigh-speed shooting capability of 1,000,000 fps was made possible by directly connecting CCD storages, which record video images, to the photodiodes of individual pixels. The number of consecutive frames was 144. However, longer capture times were demanded when the camera was used during imaging experiments and for some television programs.
To increase ultrahigh-speed capture times, we used a beam splitter and two ultrahigh-speed 300,000-pixel CCDs. The beam splitter was placed behind the pick up lens. One CCD was located at each of the two outputs of the beam splitter. The CCD driving unit was developed to separately drive two CCDs, and the recording period of the two CCDs was sequentially switched. This increased the recording capacity to 288 images, an increase of a factor of two over that of conventional ultrahigh-speed camera.
A problem with the camera was that the incident light on each CCD was reduced by a factor of two by using the beam splitter. To improve the light sensitivity, we developed a microlens array for use with the ultrahigh-speed CCDs. We simulated the operation of the microlens array in order to optimize its shape and then fabricated it using stamping technology. Using this microlens increased the light sensitivity of the CCDs by an approximate factor of two.
By using a beam splitter in conjunction with the microlens array, it was possible to make an ultrahigh-speed color video camera that has 288 frame memories but without decreasing the camera's light sensitivity.
This paper presents preliminary evaluation results of a test sensor of the backside-illuminated ISIS, an ultra-high
sensitivity and ultra-high speed CCD image sensor. To achieve ultra-high sensitivity, the CCD image sensor employs the
following three technologies: backside illumination, cooling and Charge Carrier Multiplication (CCM). The test sensor
has been designed, fabricated and evaluated. At room temperature without cooling, the video camera has about ten-time
higher sensitivity than the previous one, which was supported by a conventional front side illumination technology.
Furthermore, the video camera can detect images at very low signal level, less than 5 e-, by using CCM at -40 degree C.
A new-generation full-frame 36x48 mm2 48Mp CCD image sensor with vertical anti-blooming for professional digital
still camera applications is developed by means of the so-called building block concept. The 48Mp devices are formed
by stitching 1kx1k building blocks with 6.0 µm pixel pitch in 6x8 (hxv) format. This concept allows us to design four
large-area (48Mp) and sixty-two basic (1Mp) devices per 6" wafer. The basic image sensor is relatively small in order to
obtain data from many devices. Evaluation of the basic parameters such as the image pixel and on-chip amplifier
provides us statistical data using a limited number of wafers. Whereas the large-area devices are evaluated for aspects
typical to large-sensor operation and performance, such as the charge transport efficiency. Combined with the usability
of multi-layer reticles, the sensor development is cost effective for prototyping.
Optimisation of the sensor design and technology has resulted in a pixel charge capacity of 58 ke- and significantly
reduced readout noise (12 electrons at 25 MHz pixel rate, after CDS). Hence, a dynamic range of 73 dB is obtained.
Microlens and stack optimisation resulted in an excellent angular response that meets with the wide-angle photography
demands.
We developed and implemented a flexible image pre-processing concept to achieve an image sub-system for top-end
professional digital still camera applications that ensures the highest possible image quality. It supports high-speed
multiple-image acquisition and data processing for very-large resolution images, it reduces the design-in time for the
customers and it can be implemented economically for high-end applications with relatively smaller volumes.
This paper presents an overview of the specific challenges that need to be overcome to make very-large CCD and CMOS
imagers, and presents some recent innovations in this area. The complete development chain is described: research,
production and industrialization. It will be shown that by innovative design and technology concepts, high-quality very large
area CCD and CMOS imagers can be made, even up to wafer size (6" for CCD, 8" for CMOS).
KEYWORDS: Cameras, Charge-coupled devices, CCD cameras, Signal processing, Digital signal processing, Video, Field programmable gate arrays, Image processing, Photodiodes, Eye
We have developed an ultrahigh-speed, high-sensitivity portable color camera with a new 300,000-pixel single CCD.
The 300,000-pixel CCD, which has four times the number of pixels of our initial model, was developed by seamlessly
joining two 150,000-pixel CCDs. A green-red-green-blue (GRGB) Bayer filter is used to realize a color camera with the
single-chip CCD. The camera is capable of ultrahigh-speed video recording at up to 1,000,000 frames/sec, and small
enough to be handheld. We also developed a technology for dividing the CCD output signal to enable parallel, highspeed
readout and recording in external memory; this makes possible long, continuous shots up to 1,000 frames/second.
As a result of an experiment, video footage was imaged at an athletics meet. Because of high-speed shooting, even
detailed movements of athletes' muscles were captured. This camera can capture clear slow-motion videos, so it enables
previously impossible live footage to be imaged for various TV broadcasting programs.
This paper gives an overview of featuring possibilities in CCD imagers. By careful manipulation of charge packets in CCD imagers, a CCD can often be read out in different modes by simply modifying the applied pulse patterns. Since featuring is done in the charge domain and not in the voltage domain, it offers the best possible performance with respect to noise, dynamic range and signal-to-noise ratio.
This paper gives an overview of the requirements for, and current state-of-the-art of, CCD and CMOS imagers for use in digital still photography. Four market segments will be reviewed: mobile imaging, consumer "point-and-shoot cameras", consumer digital SLR cameras and high-end professional camera systems. The paper will also present some challenges and innovations with respect to packaging, testing, and system integration.
We are developing an ultrahigh-speed, high-sensitivity broadcast camera that is capable of capturing clear, smooth slow-motion videos even where lighting is limited, such as at professional baseball games played at night. In earlier work, we developed an ultrahigh-speed broadcast color camera1) using three 80,000-pixel ultrahigh-speed, highsensitivity CCDs2). This camera had about ten times the sensitivity of standard high-speed cameras, and enabled an entirely new style of presentation for sports broadcasts and science programs. Most notably, increasing the pixel count is crucially important for applying ultrahigh-speed, high-sensitivity CCDs to HDTV broadcasting. This paper provides a summary of our experimental development aimed at improving the resolution of CCD even further: a new ultrahigh-speed high-sensitivity CCD that increases the pixel count four-fold to 300,000 pixels.
A 28-M pixel, full-frame CCD imager with 7.2×7.2 μm2 pixel size and Bayer RGB color pattern was developed for use in professional applications. As unique option a RGB compatible binning feature was designed into this sensor. This gives the possibility to exchange resolution for sensitivity, read-out speed and signal-to-noise ratio. This paper presents the device architecture, RGB binning principle and evaluation results of the overall sensor performance. The performed device simulations and the evaluation results of the RGB binning feature are described in detail.
An image sensor for an ultra-high-speed video camera was developed. The maximum frame rate, the pixel count and the number of consecutive frames are 1,000,000 fps, 720 x 410 (= 295,200) pixels, and 144 frames. A micro lens array will be attached on the chip, which increases the fill factor to about 50%. In addition to the ultra-high-speed image capturing operation to store image signals in the in-situ storage area adjacent to each pixel, standard parallel readout operation at 1,000 fps for full frame readout is also introduced with sixteen readout taps, for which the image signals are transferred to and stored in a storage device with a large capacity equipped outside the sensor. The aspect ratio of the frame is about 16 : 9, which is equal to that of the HDTV format. Therefore, a video camera with four sensors of the ISIS-V4, which are arranged to form the Bayer’s color filter array, realizes an ultra-high-speed video camera of a semi-HDTV format.
A 1/2 inch 1M-pixel monochrome Frame-Transfer CCD imager with 5.6μm by 5.6μm pixel size was developed for use in medical and industrial applications. The sensor production uses 17 mask steps designed for an improved process, with highly transparent membrane poly-silicon gates and two metal layers. The first metal layer is used for vertical strapping to reduce the RC- times of the imaging electrodes. The image pixels, the storage cells and the readout register are made using two layers of membrane poly-silicon. An n-channel implant on a profiled p-well in a n-substrate achieves 52,000 electrons full well charge storage capacity in combination with excellent vertical anti-blooming and fast electronic shuttering. Smear as low as 0.06% at 1/30 sec integration time is achieved at 5MHz frame shift frequency. The pixel charge is converted to an output voltage using a 3-stage source follower amplifier, optimized for 40MHz pixel frequency. For use in high-speed industrial applications, the split read-out allows pixel rates up to 80MHz. The output amplifier with a conversion gain of 18.7μV/electron has an rms noise of 18 electrons at full bandwidth (linear dynamic range of 67.8 dB). The dark current level is 100 pA/cm2 at 60° C.
To meet the continuous demand for more resolution in professional digital imaging, 22M pixels, 645-film format full-frame CCD image sensor was developed as an improved upgrade for an existing 11M pixel 35 mm CCD. This paper presents the device requirements, architecture, modes of operation, and evaluation results of the performance improvements.
KEYWORDS: Sensors, Cameras, CCD cameras, Image sensors, Data storage, High speed imaging, Imaging systems, Charge-coupled devices, Computer architecture, Chemical elements
A new high-speed CCD-sensor, capable of capturing 103 consecutive images at a speed of 1 million frames per second, was developed by the authors. To reach this high frame-rate, 103 CCD-storage-cells are placed next to each image-pixel. Sensors utilizing this on-chip-memory-concept can be called In-situ Storage Image Sensor or ISIS. The ISIS is build in standard CCD-technology. To check if this technology could be used for an ISIS, a test sensor called ISIS V1 was designed first. The ISIS V1 is just a simple modification of an existing standard CCD-sensor and it is capable of taking 17 consecutive images. The new sensor called ISIS V2 is a dedicated design in the existing technology. It is equipped with storage CCD-cells that are also used in the standard CCD-sensor, large light-sensitive pixels, an overwriting mechanism to drain old image information and a CCD-switch to use a part of the storage cells also as vertical read-out registers. Nevertheless, the new parts in the architecture had to be simulated by a 3-D device simulator. Simulation results and characteristic parameters of the ISIS-CCD as well as applications of the camera are given.
A technology is described which allows the application of real-time imaging in combination with mega-pixel CCDs. This technology is based on the following characteristics: high-speed transport of the video information through the parallel CCDs in the imaging section, very high-speed transport of the charge packets through the serial section of the devices, and high- speed conversion of the electrons to a measurable voltage by the output amplifier. Key competencies to comply with these requirements are: low-resistive CCD gates, low- capacitance CCD gates and high bandwidth and low noise floor output stages.
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