In the realm of Design for Manufacturability (DFM) optimization, Pattern-Based Layout Optimization (PBLO) has been a go-to approach for detecting and repairing DFM violations. However, to enhance the effectiveness of DFM rules in addressing hotspots, it becomes imperative to encompass a broader array of design situations (layout contexts). This expansion leads to an increased number of potential fixing guidance “hints”. Nonetheless, employing a static fixing hint order, unaware to the specific in-design topologies, can potentially diminish the output metrics i.e., fixing rate and runtime performance. In pursuit of optimizing these output metrics, we present an ML-powered PBLO workflow. In this innovative approach, a Machine Learning (ML) model is trained using an extensive dataset of preranked fixing guidance hints that are associated with a DFM rule. The topology aware supervised ML model is trained to dynamically guide and select the most suitable in-design fixing guidance order per situation, ultimately leading to an improved fixing rate, runtime and quality of results. In this study, we illustrate a workflow and mechanism for seamlessly integrating machine learning capabilities into the in-design fixing router. This involves developing multiclass machine learning algorithms and models to facilitate the generation of an optimal fixing guidance sequence.
This paper demonstrates a new approach for hotspot detection in large design spaces. We present a new pattern matching technique, which is a multi-window pattern search that is deployed in a dynamic and precise way to search for similar patterns. Based on the matched locations the flow extracts and combines silicon awareness features and design level features to build comprehensive feature matrix that can be used in subsequent analytical analysis. The paper also shows the advantage of using this flow with respect to precise capture of hotspot and ~10X improvement on turnaround time for feature extraction compared with traditional methods. The output of this flow also facilitates and improves the data preparation process for machine learning model building.
Systematic defects have drawn a lot of focus from the semiconductor industry, especially in the technology development and early technology ramp. However, random defects are still dominant when the technology is mature and in highvolume manufacturing. Historically, foundries have run critical area analysis on incoming designs in order to identify the yield-limiting failure modes and estimate the yield loss. However, with growing design complexity in advanced technology nodes, the calculation runtime of critical area has increased from hours to days and even week(s). Also FINFET brings their own challenges and new failure modes such as transistor-related defectivity and inter-layer interactions. Meanwhile, it has become more and more challenging to obtain accurate defect density by failure mode. In this paper, GlobalFoundries and Cadence describe the motivations that drove their partnership to develop a new generation of critical area analysis with adaptive sampling to reduce runtime while maintaining accuracy, especially while taking into account connectivity and transistor defectivity. After reviewing the principle and challenges of critical area calculation and yield estimation, two new methodologies of yield modeling using critical area analysis are given to address these challenges. The first methodology avoids the costly and complicated process of defect density calibration. The second methodology fulfills the wafer-based yield projection with critical area normalization and machine learning.
Two-dimensional pattern matching libraries are used to define known hotspots in the design space. These libraries can then be integrated into a physical design router to search and fix such hotspots prior to the design being completed and signed off. The task of searching for similar patterns to the known hotspot involves a significant manual effort in pattern match library development. This paper demonstrates an automated and comprehensive approach to profile the available design space for similar topological patterns based on the known hotspot and automatically generate a comprehensive master pattern library to fix and address the hotspot issue. This paper presents a semi-supervised learning algorithm for developing pattern similarity metric for pattern similarity ranking and clustering.
Layout-pattern-based approaches for physical design analysis and verification have become mainstream in recent years and are enabling many new applications. Prior work introduced the ability to collect all patterns from multiple layouts into a catalog as well as to use machine learning techniques to score and filter patterns to identify which ones are critical. In this paper, data mined from a library of scored patterns from established designs is applied to the analysis of diagnosis results from a new design to improve defect root cause analysis (RCA).
The flow for this approach is as follows: patterns interacting with nets reported in diagnosis callouts are selected as patterns of interest (POIs) from the catalog of all patterns. Next, features of interest (FOIs) are extracted from all POIs to build a dataframe. Finally, volume diagnosis results identifying nets with likely open or short defects are added to the dataframe. RCA is performed using the dataframe to identify likely root cause(s) for failures and suggest refined failure locations for targeted inspection, physical failure analysis, or other electrical failure analysis.
The approach described above is applied to products in high-volume manufacturing using a leading-edge technology node. Silicon validation results will be included for example applications.
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