Electron Beam Lithography and Nanofabrications ,
Proximity Effect Correction & Data Preparation ,
Electron Beam Resist Process Development and Optimization ,
E-Beam Lithography Tool Optimization and its Performance Characterization ,
SEM based CD Metrology
A sensitivity analysis (SA) algorithm was developed and tested to comprehend the influences of different test pattern sets on the calibration of a point spread function (PSF) model with complementary approaches. Variance-based SA is the method of choice. It allows attributing the variance of the output of a model to the sum of variance of each input of the model and their correlated factors.1 The objective of this development is increasing the accuracy of the resolved PSF model in the complementary technique through the optimization of test pattern sets. Inscale® from Aselta Nanographics is used to prepare the various pattern sets and to check the consequences of development. Fraunhofer IPMS-CNT exposed the prepared data and observed those to visualize the link of sensitivities between the PSF parameters and the test pattern. First, the SA can assess the influence of test pattern sets for the determination of PSF parameters, such as which PSF parameter is affected on the employments of certain pattern. Secondly, throughout the evaluation, the SA enhances the precision of PSF through the optimization of test patterns. Finally, the developed algorithm is able to appraise what ranges of proximity effect correction is crucial on which portion of a real application pattern in the electron beam exposure.
KEYWORDS: Metals, Semiconducting wafers, Electron beam lithography, Etching, Electron beam direct write lithography, Photomasks, Optical alignment, Wafer-level optics, Back end of line, Electron beams
Electron beam direct write lithography (EBDW) potentially offers advantages for low-volume semiconductor manufacturing, rapid prototyping or design verification due to its high flexibility without the need of costly masks.
However, the integration of this advanced patterning technology into complex CMOS manufacturing processes remains challenging. The low throughput of today’s single e-Beam tools limits high volume manufacturing applications and maturity of parallel (multi) beam systems is still insufficient [1,2]. Additional concerns like transistor or material damage of underlying layers during exposure at high electron density or acceleration voltage have to be addressed for advanced technology nodes. In the past we successfully proved that potential degradation effects of high-k materials or ULK shrink can be neglected and were excluded by demonstrating integrated electrical results of 28nm node transistor and BEOL performance following 50kV electron beam dry exposure [3].
Here we will give an update on the integration of EBDW in the 300mm CMOS manufacturing processes of advanced integrated circuits at the 28nm SRAM node of GLOBALFOUNDRIES Dresden. The work is an update to what has been previously published [4]. E-beam patterning results of BEOL full chip metal and via layers with a dual damascene integration scheme using a 50kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMSCNT are demonstrated. For the patterning of the Metal layer a Mix & Match concept based on the sequence litho - etch -litho -etch (LELE) was developed and evaluated wherein several exposure fields were blanked out during the optical exposure. Etch results are shown and compared to the POR. Results are also shown on overlay performance and optimized e-Beam exposure time using most advanced data prep solutions and resist processes. The patterning results have been verified using fully integrated electrical measurement of metal lines and vias on wafer level.
In summary we demonstrate the integration capability of EBDW into a productive CMOS process flow at the example of the 28nm SRAM technology node.
KEYWORDS: Metals, Etching, Semiconducting wafers, Optical alignment, Electron beam direct write lithography, Photomasks, Back end of line, Electron beam lithography, Scanning electron microscopy, Electron beams
Many efforts were spent in the development of EUV technologies, but from a customer point of view EUV is still behind expectations. In parallel since years maskless lithography is included in the ITRS roadmap wherein multi electron beam direct patterning is considered as an alternative or complementary approach for patterning of advanced technology nodes. The process of multi beam exposures can be emulated by single beam technologies available in the field. While variable shape-beam direct writers are already used for niche applications, the integration capability of e-beam direct write at advanced nodes has not been proven, yet. In this study the e-beam lithography was implemented in the BEoL processes of the 28nm SRAM technology. Integrated 300mm wafers with a 28nm back-end of line (BEoL) stack from GLOBALFOUNDRIES, Dresden, were used for the experiments. For the patterning of the Metal layer a Mix and Match concept based on the sequence litho - etch - litho – etch (LELE) was developed and evaluated wherein several exposure fields were blanked out during the optical exposure. E-beam patterning results of BEoL Metal and Via layers are presented using a 50kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMS-CNT. Etch results are shown and compared to the POR. In summary we demonstrate the integration capability of EBDW into a productive CMOS process flow at the example of the 28nm SRAM technology node.
A new correction technique has been developed not only to reduce the corner rounding, but also to restrain the
building up of shot counts that is able to increase the exposure time in electron beam (e-beam) lithography. It is able to
prove the developed corner rounding correction technique is useful with high accuracies throughout the simulation of
several different types of correction in the data preparation software, Inscale® from Aselta Nanographics, and its
comparisons with exposure images. The developed one is helpful to suppress the accumulation of shot counts either.
Furthermore, it shows the general limit of corner rounding correction in a conventional variable shaped beam exposure
tool with current resist process. Firstly, we are demonstrating the new method for correcting the corner rounding that
either can avoid the extension of exposure shot counts, called writing time. Secondly, this study reveals the current
bounds of corner rounding correction, especially the lithography employing the shaped beam tool. Finally, we propose
the criteria of data preparation for the corner rounding in e-beam lithography, specifically upcoming 18nm technology
node and practical applications.
Proximity Effects in electron beam lithography impact feature dimensions, pattern fidelity and uniformity. These effects
are addressed using a mathematical model representing the radial exposure intensity distribution induced by a point
electron source, commonly named as the Point Spread Function (PSF). PSF models are usually employed for predicting
and compensating for effects up to 15μm. It is well known that there are also some process related phenomena that
impact pattern uniformity that have a longer range, namely CMP effects, fogging, etc.
Performing proximity effects corrections can result in lengthy run times as file size and pattern densities continue to
increase exponentially per technology node. Running corrections for extreme long range phenomena becomes
computational and file size prohibitive. Nevertheless, since extreme long range may reach up several millimeters, and
new technology nodes require a high level of precision, a strategy for predicting and compensating these phenomena is
crucial.
In this paper a set of test patterns are presented in order to verify and calibrate the so called extreme long range effects in
the electron beam lithography. Moreover, a strategy to compensate for extreme long range effects based on the pattern
density is presented. Since the evaluation is based on a density map instead of the actual patterns, the computational
effort is feasible.
The proposed method may be performed off-line (in contrast to machine standard in-line correction). The advantage of
employing off-line compensation relies on enhancing the employ of dose and/or geometry modulation. This strategy also
has the advantage of being completely decoupled from other e-beam writer’s internal corrections (like Fogging Effect
Correction - FEC).
KEYWORDS: Calibration, Metrology, Semiconducting wafers, Error analysis, Process modeling, Data modeling, Point spread functions, Opacity, Electron beam lithography, Statistical modeling
In electron proximity effects correction (PEC), the quality of a correction is highly dependent on the quality of the model
used to compute the effects. Therefore it is of primary importance to have a reliable methodology to extract the
parameters and assess the quality of a model. Usually, model calibration procedures consist of one or more cycles of
exposure and measurements on the calibration stage. The process and metrology variability may play a key role in the
quality of the final model and, hence, of the PEC result. Therefore, it is important to determine at which level these
variations may impact a calibration procedure and how a calibration design may be implemented in order to enable more
robustness to the resulting model.
In this work, metrology variability was evaluated by measuring the same wafer using two different CD-SEM tools. The
information coming from these analyses was used as reference to a variation induced calibration test using synthetic
data. By inserting variability in synthetic data it was possible to evaluate its impact on the resulting parameter values and
in the final model error evaluation.
KEYWORDS: Silicon, Semiconducting wafers, System on a chip, Aluminum, Titanium, Scattering, Point spread functions, Metals, Neodymium, Electron beam lithography
Resist processing for future technology nodes becomes more and more complex. The resist film thickness is getting thinner and hardmask concepts (trilayer) are needed for reproducible etch transfer into the stack. Additional layers between resist and substrate are influencing the electron scattering in e-beam lithography and may also improve sensitivity and resolution. In this study, bare silicon wafers with different assisting underlayers were processed in a 300 mm CMOS manufacturing environment and were exposed on a 50 keV VISTEC SB3050DW variable-shaped electron beam direct writer at Fraunhofer CNT. The underlayers are organic-inorganic hybrid coatings with different metal additives. The negative-tone resist was evaluated in terms of contrast, sensitivity, resolution and LWR/LER as a function of the stack. The interactions between resist and different assisting underlayers on e-beam direct writing will be investigated. These layers could be used to optimize the trade-off among resolution, LWR and sensitivity in future applications.
KEYWORDS: Back end of line, Transistors, Semiconducting wafers, Dielectrics, Oxides, Resistance, Copper, Electron beam lithography, Capacitance, Metals
While significant resources are invested in bringing EUV lithography to the market, multi electron beam direct
patterning is still being considered as an alternative or complementary approach for patterning of advanced technology
nodes. The possible introduction of direct write technology into an advanced process flow however may lead to new
challenges. For example, the impact of high-energy electrons on dielectric materials and devices may lead to changes in
the electrical parameters of the circuit compared to parts conventionally exposed by optical lithography. Furthermore,
degradation of product reliability may occur. These questions have not yet been clarified in detail.
For this study, pre-structured 300mm wafers with a 28nm BEOL stack were dry-exposed at various processing levels
using a 50kV variable shaped e-beam direct writer. The electrical parameters of exposed structures were compared to
non-exposed structures. The data of line resistance, capacitance, and line to line leakage were found to be within the
typical distributions of the standard process. The dielectric breakdown voltages were also comparable between the splits,
suggesting no dramatic TDDB performance degradation. With respect to high-k metal gate transistor parameters, a
decrease in threshold voltage shift sensitivity was observed as well as a reduced sensitivity to hot carrier injection. More detailed investigations are needed to determine how these findings need to be considered and whether they represent a risk for the introduction of maskless lithography into the process flow of advanced technology nodes.
In electron proximity effect correction (PEC), the quality of a correction is highly dependent on the quality of the model.
Therefore it is of primary importance to have a reliable methodology to extract the parameters and assess the quality of a
model. Among others the model describes how the energy of the electrons spreads out in the target material (via the
Point Spread Function, PSF) as well as the influence of the resist process. There are different models available in
previous studies, as well as several different approaches to obtain the appropriate value for their parameters. However,
those are restricted in terms of complexity, or require a prohibitive number of measurements, which is limited for a
certain PSF model.
In this work, we propose a straightforward approach to obtain the value of parameters of a PSF. The methodology is
general enough to apply for more sophisticated models as well. It focused on improving the three steps of model
calibration procedure: First, it is using a good set of calibration patterns. Secondly, it secures the optimization step and
avoids falling into a local optimum. And finally the developed method provides an improved analysis of the calibration
step, which allows quantifying the quality of the model as well as enabling a comparison of different models. The
methodology described in the paper is implemented as specific module in a commercial tool.
Using electron beam direct write (EBDW) as a complementary approach together with standard optical lithography at
193nm or EUV wavelength has been proposed only lately and might be a reasonable solution for low volume CMOS
manufacturing and special applications as well as design rule restrictions. Here, the high throughput of the optical litho
can be combined with the high resolution and the high flexibility of the e-beam by using a mix & match approach (Litho-
Etch-Litho-Etch, LELE). Complementary Lithography is mainly driven by special design requirements for unidirectional
(1-D gridded) Manhattan type design layouts that enable scaling of advanced logic chips. This requires significant data
prep efforts such as layout splitting.
In this paper we will show recent results of Complementary Lithography using 193nm immersion generated 50nm
lines/space pattern addressing the 32nm logic technology node that were cut with electron beam direct write. Regular
lines and space arrays were patterned at GLOBALFOUNDRIES Dresden and have been cut in predefined areas using a
VISTEC SB3050DW e-beam direct writer (50KV Variable Shaped Beam) at Fraunhofer Center Nanoelectronic
Technologies (CNT), Dresden, as well as on the PML2 tool at IMS Nanofabrication, Vienna. Two types of e-beam
resists were used for the cut exposure. Integration issues as well as overlay requirements and performance improvements
necessary for this mix & match approach will be discussed.
To fulfill the requirements of future technology nodes new resists with high resolution, high sensitivity and low
LWR and LER respectively are needed. A new inorganic non-chemically amplified resist (XE15IB, an experimental
resist provided by Inpria Corp.) was investigated. The resist is spin-cast from aqueous solution and is
based on hafnium oxide. Metal oxide based resist as XE15IB supersede other resist materials due to its high
etch resistance.1, 2 This new material can be considered as a direct patternable spin on hard mask.
XE15IB was processed in a 300mm complementary metal oxide semiconductor (CMOS) manufacturing environment
and exposed on a 50 kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer
Center Nanoelectronic Technologies (CNT).
The resist was evaluated in terms of contrast, sensitivity and resolution. The process characteristics required
for CMOS manufacturing such as delay stability were also examined. Furthermore, by printing a large static
random access Memory (SRAM) pattern (design CD of 22 nm), the exposure of a real application pattern was
demonstrated.
A new correction approach was developed to improve the process window of electron beam lithography and push its
resolution at least one generation further using the same exposure tool. An efficient combination of dose and geometry
modulation is implemented in the commercial data preparation software, called Inscale®, from Aselta Nanographics.
Furthermore, the electron Resolution Improvement Feature (eRIF) is tested, which is based on the dose modulation and
multiple-pass exposure, for not only overcoming the narrow resist process windows and disability of exposure tool but
also more accurate correction of exposure data in the application of sub-35nm regime. Firstly, we are demonstrating the
newly developed correction method through the comparison of its test exposure and the one with conventional dose
modulation method. Secondly, the electron Resolution Improvement Feature is presented with the test application for
complementary exposure and with the application of real design, specifically for sub-30nm nodes. Finally, we discuss
the requirements of data preparation for the practical applications in e-beam lithography, especially for future technology
nodes.
For the manufacturing of semiconductor technologies following the ITRS roadmap, we will face nodes well below a 32-nm half pitch in the next 2 to 3 years. Despite being able to achieve the required resolution, which is now possible with electron beam direct-write variable-shaped beam equipment and resists, it becomes critical to precisely reproduce dense line space patterns onto a wafer. This exposed pattern must meet the targets from the layout in both dimensions (horizontally and vertically). For instance, the end of a line must be printed in its entire length to allow a contact to be placed later. Up to now, the control of printed patterns such as line ends was achieved by a proximity effect correction mostly based on a dose modulation. This investigation of line end shortening (LES) includes multiple novel approaches, and contains an additional geometrical correction to push the limits of the available data preparation algorithms and the measurement. The designed LES test patterns, which aim to characterize the status of LES in a quick and easy way, were exposed and measured at Fraunhofer Center Nanoelectronic Technologies using its state-of-the-art electron beam direct writer and CD-SEM. Simulation and exposure results with the novel LES correction algorithms applied to the test pattern and a large production-like pattern in the range of our targeted critical structure dimensions in dense line space features smaller than 40 nm will be shown.
Electron Beam Direct Write (EBDW) lithography is used in the IC manufacturing industry to sustain optical
lithography for prototyping applications and low volume manufacturing. It is also used in R&D to develop advanced
technologies, ahead of mass production. As microelectronics is now moving towards the 32nm node and beyond, the
specifications in terms of dimension control and roughness becomes tighter. In addition, the shrink of the size and pitch
of features significantly reduces the process window of lithographic tools. In EBDW, the standard proximity effects
corrections only based on dose modulation show difficulties to provide the required Energy Latitude for patterning
structures designed below 45nm. A new approach is thus needed to improve the process window of EBDW lithography
and push its resolution capabilities.
In previous papers, a new writing strategy based on multiple pass exposure has been introduced and optimized to
pattern critical dense lines. This new technique consists in adding small electron Resolution Improvement Features
(eRIFs) on top of the nominal structures. Then this new design is exposed in two successive passes with optimized doses.
Previous studies were led to evaluate this new writing technique and establish rules to optimize the design of the eRIF.
Significant improvements have already been demonstrated on SRAM and Logic structures down to the 16nm node.
These results were obtained with a tool dedicated to the 45nm node. The next step of this work is thus to automatically
implement the eRIF to correct large-scale layouts.
In this paper, a new data preparation flow is set up for EBDW lithography. It uses the eRIF solution as a full
advanced correction method for critical structures. The specific correction rules established in our previous studies are
implemented to improve the CD control and the patterning of corners and line ends. Moreover, the dose and shape of the
eRIFs are automatically tuned to best fit the nominal design. This work is done with "INSCALE®", the new data
preparation software from ASELTA Nanographics. This data preparation flow is then applied on layouts down to the
22nm node. Comparisons with the standard dose modulation flow demonstrate that adding eRIFs significantly improves
the process window and thus the resolution of e-beam tools. It also shows that the multiple pass exposure technique can
be used as a specific correction method on large scale layouts.
KEYWORDS: Cadmium sulfide, Computer simulations, Semiconducting wafers, Electron beam lithography, Electron beams, Detection and tracking algorithms, Point spread functions, Electron beam direct write lithography, Modulation, Nanoelectronics
For the manufacturing of semiconductor technologies following the ITRS roadmap, we will face the nodes well below
32nm half pitch in the next 2~3 years. Despite being able to achieve the required resolution, which is now possible with
electron beam direct write variable shaped beam (EBDW VSB) equipment and resists, it becomes critical to precisely
reproduce dense line space patterns onto a wafer. This exposed pattern must meet the targets from the layout in both
dimensions (horizontally and vertically). For instance, the end of a line must be printed in its entire length to allow a later
placed contact to be able to land on it. Up to now, the control of printed patterns such as line ends is achieved by a
proximity effect correction (PEC) which is mostly based on a dose modulation.
This investigation of the line end shortening (LES) includes multiple novel approaches, also containing an additional
geometrical correction, to push the limits of the available data preparation algorithms and the measurement. The
designed LES test patterns, which aim to characterize the status of LES in a quick and easy way, were exposed and
measured at Fraunhofer Center Nanoelectronic Technologies (CNT) using its state of the art electron beam direct writer
and CD-SEM.
Simulation and exposure results with the novel LES correction algorithms applied to the test pattern and a large
production like pattern in the range of our target CDs in dense line space features smaller than 40nm will be shown.
For current and future semiconductor technology nodes with critical dimensions of 32 nm or below, the e-beam
lithography is faced with increasing challenges to achieve a reasonable patterning of structures, especially if a process
with a chemically amplified resist is used. The reasons for these limitations are the physical properties of the transfer
process used to print a structure onto the resist-coated substrate, which inherently contains an unavoidable blurring of the
deposited e-beam energy around the desired shape. This blurring is usually described by a so called process proximity
function (PPF) and mostly approximated by a superposition of two or more Gaussian functions. The PPF includes the e-beam
blur, electron forward scattering and resist effects (often described altogether by the so called alpha parameter of
the PPF [K. Keil et al, "Resolution and total blur: Correlation and focus-dependencies in e-beam lithography," J. Vac.
Sci. Technol. B 27, 2722 (2009)]) as well as the backscattering effect (often described by the so called beta parameter of
the PPF). When the desired critical dimensions of structures are near or below the alpha parameter of the PPF, depending
on their environment it may be just impossible to print the structures because of the vanishing image contrast. The PPF
model confirms this well-known behavior but also shows ways and limits for improvements.
This paper provides real pattern lithography results - comparing classical and GIDC correction - for exposures done on a
Vistec SB3050DW shaped e-beam writer. A performance comparison of the GIDC method and the classical dose
correction in terms of data preparation and writing time is presented.
KEYWORDS: Semiconducting wafers, Computer simulations, Cadmium, Modulation, Detection and tracking algorithms, Electron beam lithography, Electron beams, Electron beam direct write lithography, Point spread functions, Nanoelectronics
For the manufacturing of semiconductor technologies following the ITRS roadmap, we will face the nodes well below
32nm half pitch in the next 2~3 years. Despite being able to achieve the required resolution, which is now possible with
electron beam direct write variable shaped beam (EBDW VSB) equipment and resists, it becomes critical to precisely
reproduce dense line space patterns onto a wafer. This exposed pattern must meet the targets from the layout in both
dimensions (horizontally and vertically). For instance, the end of a line must be printed in its entire length to allow a later
placed contact to be able to land on it. Up to now, the control of printed patterns such as line ends is achieved by a
proximity effect correction (PEC) which is mostly based on a dose modulation.
This investigation of the line end shortening (LES) includes multiple novel approaches, also containing an additional
geometrical correction, to push the limits of the available data preparation algorithms and the measurement. The
designed LES test patterns, which aim to characterize the status of LES in a quick and easy way, were exposed and
measured at Fraunhofer Center Nanoelectronic Technologies (CNT) using its state of the art electron beam direct writer
and CD-SEM.
Simulation and exposure results with the novel LES correction algorithms applied to the test pattern and a large
production like pattern in the range of our target CDs in dense line space features smaller than 40nm will be shown.
The e-beam lithography is faced with increasing challenges to achieve a satisfying patterning of structures with critical dimensions of
about 32 nm or below. The reason for this issue is the unavoidable blurring of the deposited e-beam energy due to beam blur, electron
scattering (forward and backward), and resist effects. The distribution of the finally deposited dose differs from the dose weighted
geometry of the printed layout. In general, the finally deposited dose is described as convolution of the layout with a process specific
proximity function being a model for the unavoidable blurring. This process proximity function (PPF) is often approximated by a
superposition of two or more Gaussian functions. Thus, the electron forward scattering and resist effects, being most critical to the
pattern fidelity, are often described altogether by the so called alpha-parameter of the PPF. Due to these physical reasons, when the
desired critical dimension of a structure is near or below the alpha-parameter of the PPF, it may be just impossible to print the
structure because of the vanishing image contrast due to the blurring.
It was shown by means of the simulation feature of the ePLACE data prep package that in this situation a modification of both the
geometry and the dose assignment of the shapes will significantly increase the contrast of the deposited energy and thus, even preserve
the printability of critical structures. This geometrically induced dose correction (GIDC) method is implemented in the ePLACE
package. The simulation results for test structures are now validated by exposures of test patterns and its results clearly establish the
practical advantage of the new method.
In this paper we will publish the results of the related exposures - done on Vistec SB3050 series shaped e-beam writers -
demonstrating the practical importance of the GIDC method for layouts with critical dimensions of 32 nm and below.
KEYWORDS: Calibration, Monte Carlo methods, Photoresist processing, Electron beam lithography, Data modeling, Process modeling, Scanning electron microscopy, Computer simulations, Scattering, Chemically amplified resists
With the constantly improving maturity of e-beam direct write exposure tools and processes for applications in high volume
manufacturing, new challenges with regard to speed, throughput, correction and verification have to be faced. One objective
of the MAGIC high-throughput maskless lithography project [1] is the application of the physics-based simulation in a
virtual e-beam direct write environment to investigate proximity effects and develop comprehensive correction
methodologies [2]. To support this, a rigorous e-beam lithography simulator for the feature scale has been developed [3]. The
patterning behavior is determined by modeling electron scattering, exposure, and resist processing inside the film stack, in
analogy with corresponding simulation capabilities for the optical and EUV case. Some model parameters, in particular for
the resist modeling cannot be derived from first principles or direct measurements but need to be determined through a
calibration process.
To gain experience with the calibration of chemically amplified resists (CAR) for e-beam lithography, test pattern exposures
have been performed for a negative tone CAR using a variable-shaped beam writer operating at 50kV. A recently
implemented model calibration methodology has been applied to determine the optimum set of resist model parameters.
While the calibration is based on 1D (lines & spaces) patterns only, the model results are compared to 2D test structures for
verification.
KEYWORDS: Electron beam direct write lithography, Cadmium sulfide, Image processing, Printing, Line width roughness, Line edge roughness, Electron beams, Point spread functions, Photoresist processing, Metrology
For shortening the writing time, especially in shaped Electron Beam Direct Writing (EBDW), it is crucial to reduce
the number of shapes and the coverage of layout for exposure. The determination of conventional or reversed image
printing according to the process integration is one of the concerns for time and cost-effective process in the EBDW. We
have studied two different cases for the purpose above. First, the proximity effect correction (PEC) with dose
modification applied on each tone of resists, positive and negative, for the printing of conventional and reversed images.
The CDs that are obtained from the both printed images compared and are either with that from the simulations.
Secondly, the two different types of PEC, dose and shape modification, applied to a conventional image using an
identical point spread function (PSF). The line edge roughness (LER), line width roughness (LWR) and CDs in dose and
shape corrected conventional image pattern have been measured and compared. The MGS/PROXECCO was used for all
the preparation of exposure data mentioned above. In summary, we suggest the strategies of efficient PEC for the EBDW of contrasting images, propose the available method of PEC for the time-efficient EBDW, and for the further multiple EBDW developments.
Because of mask cost reduction, electron beam direct write (EBDW) is implemented for special applications such as rapid prototyping or small volume production in semiconductor industry. One of the most promising applications for EBDW is design verification by means of metal fix. Due to write time constrains, Mix & Match solutions have to be developed at smaller nodes. This study reports on several Mix and Match processes for the integration of E-Beam lithography into the optical litho process flow of Qimonda's 70 nm and 58 nm DRAM nodes. Different metal layers have been patterned in part with DUV litho followed by E-Beam litho using a 50 kV Vistec SB3050 shaped electron beam direct writer. All hardmask patterns were then simultaneously transferred into the DRAM stack. After full chip processing a yield study comprising electrical device characterization and defect investigation was performed. We show detailed results including CD and OVL as well as improvements of the alignment mark recognition. The yield of the E-Beam processed chips was found to be within the range of wafer-to-wafer fluctuation of the POR hardware. We also report on metal fix by electrical cutting of selected diodes in large chip scales which usually cannot be accessed with FIB methods. In summary, we show the capability of EBDW for quick and flexible design verification.
KEYWORDS: Scatterometry, Metrology, Line edge roughness, Critical dimension metrology, Line width roughness, Semiconducting wafers, Electron beams, Electron beam direct write lithography, Lithography, Cadmium
Electron beam direct write (EBDW) can be utilized for developing metrology methods for future technology nodes. Due
to its advantage of high resolution and flexibility combined with suitable throughput capability, variable-shaped E-Beam lithography is the appropriate method to fabricate sub 40nm resist structures with accurately defined properties, such as critical dimension (CD), pitch, line edge roughness (LER) and line width roughness (LWR). In this study we present results of exposure experiments intended to serve as an important instrument for testing and fitting various metrology
and defect density measurement methods for future technology nodes. We successfully fabricated sub 40nm gratings with varying CD, pitch, programmed defects and LER/LWR. First metrology measurements by means of optical scatterometry on these dense structures show that variation of the signal response is sufficient to detect sub 10nm fluctuations with a satisfying repeatability.
The resolution of a variable shaped beam writer is typically given for the standard geometries like isolated line, isolated
space, and dense (1:1) line/space pattern. It is related to the imaging power of both the tool itself as well as the resist
process. In this paper we concentrate on small shots with dimensions smaller than the resolution limit, butting to a larger
shot. We show experimentally that for a line resolution of 40 nm the resolution for butting sub resolution shots can be as
small as 20 nm.
With the willingness of the semiconductor industry to push manufacturing costs down, the mask
less lithography solution represents a promising option to deal with the cost and complexity concerns
about the optical lithography solution. Though a real interest, the development of multi beam tools still
remains in laboratory environment. In the frame of the seventh European Framework Program (FP7), a
new project, MAGIC, started January 1st 2008 with the objective to strengthen the development of the
mask less technology. The aim of the program is to develop multi beam systems from MAPPER and
IMS nanofabrication technologies and the associated infrastructure for the future tool usage. This paper
draws the present status of multi beam lithography and details the content and the objectives of the
MAGIC project.
KEYWORDS: Line edge roughness, Line width roughness, Electron beam direct write lithography, Amplifiers, Metrology, Cadmium, Electron beams, Lithography, Critical dimension metrology, Modulation
Line edge roughness (LER) and line width roughness (LWR) have raised questions and concerns as current
lithography techniques reduce critical dimensions (CD) below 50 nm. There are few applications of controlled variation
of LER and LWR, even among those which use electron beam direct writing (EBDW), although it is highly desirable to
test the influence of systematical variation of LER and LWR on actual semiconductor devices. To get a clear
understanding how and what the LERs and LWRs are influencing in EBDW, we have designed and fabricated transistor
gates with programmed LER and LWR using EBDW and observed those based on CD-SEM metrology. The obtained
results including calculated power spectrum density (PSD) shows the capability of EBDW to control the LER/LWR.
Further, the influence of edge/width roughness in EBDW on device characteristics is reviewed and it gives how the
effect of LWR/LER translates to device performance in DRAM process flow. It is found that the control of LWR is more
important than that of LER for future lithography developments.
Frank Thrum, Johannes Kretz, Tarek Lutz, Katja Keil, Christian Arndt, Kang-Hoon Choi, Ulrich Baetz, Nikola Belic, Melchior Lemke, Ulrich Denker, Juergen Gramss, Karl-Heinz Kliem
If electron beam technology is used for direct writing on Si wafers (synonym EBDW) there have to be taken into account a number of specific issues concerning the layout data preparation differing considerably from those of mask writing. This is especially true because EBDW enables the most advanced technology levels which are in general one or two nodes ahead of the mainstream optical lithography.
Consequently we will have to face up to additional challenges, such like high resolution and the corresponding CD - control parameters. In order to achieve acceptable turn around times the shaped beam writers have proven to be the tool of choice. To demonstrate this behind a practical background we describe our experiences collected during 300mm wafer exposures with a SB351/3050 tool installed at the Fraunhofer Center Nanoelectronic Technology (CNT) in Dresden/Germany. Appropriate solutions are presented showing how to execute such procedures like layout fracturing and Proximity Effect Correction (PEC) of high-density layouts on a Linux computing cluster. The CD accuracy of lines being of particular interest in connection with sub 50 nm patterns being analyzed and a new model-based method allowing the reduction of the before mentioned effect is evaluated.
In any case, whether it is about short or time-consuming exposures, a precise forecast of the total processing time of the wafer in the e-beam exposure tool is of great importance. Practical findings from the use of a simulation tool specifically developed for this purpose are discussed in this paper.
E-beam direct writing, one node ahead of advanced optical lithography, can be a time and cost effective option for early device and technology development as well as for fast prototyping. Because of the device complexity only a variable-shaped e-beam writer combined with sensitive chemically amplified resists (CAR) can be considered for this approach. We evaluated various pCARs and nCARs of all major suppliers for our goal to structure DRAMs of the 50nm node using the Leica SB350 e-beam writer. The most promising samples were selected for a process optimization by variation of bake and development conditions. Finally, one resist of each tonality met the most of our specifications like dense lines and contact holes resolution, sensitivity and vacuum stability.
Multicolored electroluminescent (EL) devices has been realized utilizing poly((1-dodecyloxy-4-methyl-1,3- phenylene)(2,5"-terthienylene)) (mPTTh) as an emitting layer and tris(8-hydroxyquinoline) aluminum (Alq3) as an electron transport layer. A single layer EL device of mPTTh polymer emits orange-colored light. EL intensity increase as the thickness of Alq3 layer increases up to 30 nm, but the emission color becomes diversified when the Alq3 layer thickness is greater than 30 nm since the relative peak intensity of green EL from Alq3 layer grows. EL color is changed form orange to greenish orange depending on the thickness of Alq3 layer. EL efficiency of the double layer device was greatly enhanced by 3000 times in compared to that of single layer device. Alq3 layer in device acts as a hole blocking electron transporting layer and an emitting layer as a function of the thickness of Alq3 layer.
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