We propose a character size optimization technique to enhance throughput of multi-column-cell (MCC) lithographic systems
in which transistor patterns are projected with multiple column cells in parallel. Each and every column cell is
capable of projecting patterns with character projection (CP) and variable shaped beam (VSB) methods. Seeking the optimal
character size of characters contributes to minimizing the number of EB shots and reducing the fabrication cost for
ICs. Experimental results show that the character size optimization technique reduced 70.6% of EB shots in the best case
with an available electron beam size.
The character projection (CP) lithography is utilized for maskless
lithography (ML2) and is a potential for the future photomask
manufacture. The drawback of the electron beam (EB) lithography is
its low throughput and leads to a rise in IC prices. The number of EB
shots to project an IC chip determines the fabrication time and the
amortization cost and must be reduced. A multi-column-cell (MCC)
system is a lithographic one in which column-cells can independently
project patterns onto a silicon wafer in parallel with the CP and
variable shaped beam (VSB) lithographies. This paper presents a
technology mapping technique for enhancing the throughput of MCC
systems. Our technique enhances the throughput of MCC systems by
reducing the number of EB shots to project an entire IC chip. The
target MCC system for which our technology mapping optimizes a circuit
is the one which has not uniform but multiform CP masks among
column-cells. Such an MCC system can project more cell functions with
the CP than a uniform CP masks-based system. Comparing with an
conventional technique, our technique has achieved a 19.8% smaller
number of EB shots without any performance degradation of ICs under a
timing constraint. Moreover, our technique has achieved a 33.4%
smaller number of EB shots under no performance constraints. Our
technique is easy for both IC designers and equipment developers to
adopt because it is a software approach with no additional
modification on character projection equipment.
The character projection (CP) is utilized for maskless lithography and is a potential for the future photomask manufacture because the CP lithography can project ICs much faster than point beam projection or variable-shaped beam (VSB) projection. In this paper, we present CP mask optimization for multi-column-cell (MCC) systems, in which column-cells can project patterns in parallel with the CP and the VSB, so that their throughput is maximized. This paper presents an MINLP (mixed integer nonlinear programming) model as well as an MIP (mixed integer programming) model for optimizing a CP mask set of an MCC projection system so that projection time is minimized. The experimental results show that our optimization has achieved 71.3% less projection time for a two-column-cell system than that for a single-column-cell (SCC) system. For the two-column-cell system, it has also achieved 42.6% less projection time than a naive CP mask development approach. The experimental results denote that our optimization achieves projection time reduction more than parallelizing two column-cells by virtually increasing logic cells which are placed on CP masks and decreasing VSB projection.
The character projection (CP) is utilized for maskless lithography and is a potential for the future photomask manufacture because the CP can project ICs faster than the point beam projection and the variable-shaped beam (VSB) projection. The drawback of the CP is its lower throughput than that of photomask-based lithography and the amortization cost of CP equipment leads to the price rise of ICs. This paper discusses a CP mask development methodology for increasing the throughput of MCC systems. The proposed methodology virtually increases the number of the logic cells which are projected with the CP. In the proposed methodology, the multiform CP masks are utilized among the column-cells for reducing the VSB projection. The experimental results show that the proposed CP mask development methodology reduced 71.3% of the number of EB shots needed for an SCC system. It also reduced 42.6% of the number of EB shots needed for the MCC system in which uniform CP masks are utilized for all column-cells.
The character projection is utilized for maskless lithography and is a potential for the future photomask manufacture. The drawback of the character projection is its low throughput and leads to a price rise of ICs. This paper discusses a technology mapping technique for enhancing the throughput of the character projection. The number of EB shots to draw an entire chip determines the fabrication time for the chip. Reduction of the number of EB shots, therefore, increases the throughput of character projection equipment and reduces the cost to produce ICs. Our technology mapping technique aims to reduce the number of EB shots to draw an entire chip for increasing the throughput of character projection equipment. Our technique treats the number of EB shots as an objective to minimize. Comparing with an conventional technology mapping, our technology mapping technique achieved 19.6% reduction of the number of EB shots without any performance degradation of ICs. Moreover, our technology mapping technique achieved 48.8% reduction of the number of EB shots under no
performance constraints. Our technique is easy for both IC designers and equipment developers to adopt because it is a software approach with no additional modification on character projection equipment.
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