The fabrication of 3D high aspect ratio structures with positively sloped profiles has found extensive
applications both in the front-end and in the back-end semiconductor manufacturing. Often, high etch rates
are required and plasma etching processes with F-based chemistries need to be employed. However, plasma
etching of silicon in F-based chemistries generally results in so-called "cusping" due to its isotropic nature.
Of particular interest are the etch profiles with slope angles in the range of 50-80o and without "cusping" at
the top portion of etched structures. For 3D packaging applications, for example, even small cusping could
degrade the step-coverage of diffusion barrier layer and metal seed layer and cause void formation in
subsequent metal filling processes.
At Oerlikon USA Inc., a proprietary process scheme has been developed to etch deep and positively sloped
silicon structures (vias, trenches, etc.) at high etch rates while eliminating cusping with precise profile
control. The new process scheme employs main plasma etch steps using gas mixtures and deposition pulse
steps. And the deposition pulses intermittently punctuate the main etch steps. Using standard gases, such as
SF6 and C4F8, sloped Si trenches with slope angle of ~60o are etched in both 6" and 8" wafers, at etch rates
of ~7.0 (micron)m/min. Etch selectivity to photoresist mask materials exceeds 100:1. The process scheme and
underlying mechanism will be presented in this work.
KEYWORDS: Etching, Plasma, Silicon, Time division multiplexing, Signal processing, Semiconducting wafers, Plasma etching, Spectroscopy, Chemical analysis, Signal to noise ratio
During the fabrication of many MEMs devices it is required to etch a layer of material to completion stopping on the layer below (e.g. Silicon on Insulator (SOI) - clearing a Si layer stopping on an underlying silicon dioxide layer). Allowing the etch process to proceed beyond the time when the first layer has been removed can result in reduced thickness of the underlying stop layer, or feature profile degradation (known as "notching" for SOI applications). One method commonly used to detect plasma process termination times is optical emission spectrometry (OES). OES analyzes the light emitted from a plasma source to draw inferences about the chemical and physical state of the plasma process. In semiconductor processing this technique is commonly used to detect material interfaces during plasma etch processes. While this approach works well for single step processes or process with a limited number of discrete etch steps (such as an etch initiation followed by a main etch) it is difficult to apply OES techniques to plasma processes with rapid and periodic plasma perturbations such as time division multiplex (TDM) plasma etching processes for Si etching. At Unaxis USA, we have developed a proprietary optical emission end point algorithm in conjunction with OES to detect material transitions in TDM processes. This technique requires no synchronization of the algorithm to the TDM process and has been applied to silicon on insulator (SOI) structures. The mechanism and performance of the algorithm will be discussed. The sensitivity of the technique has been evaluated over a range of silicon etch loads. Signal to Noise (SNR) ratios of greater than 15:1 have been achieved for samples with less than 10% exposed silicon.
Time division multiplexed (TDM) plasma etch processes have found widespread applications in Micro-Electro-Mechanical Systems (MEMS) device manufacturing. Very often, silicon-on-insulator (SOI) structures are used in MEMS applications with oxide layers used as etch stop/sacrificial layers as well as device function layers. Apart from the conventional requirements for deep silicon etch including high rate, selectivity and sidewall smoothness. SOI structures require finished etches to be free of undercut, commonly referred to as notching, at the silicon/oxide interface. Notching is aggravated due to the aspect ratio dependence (ARDE) effects. The ARDE effects cause structures with different aspect ratio to be etched at different etch rates, and result in the buried oxide layer in bigger features to be exposed while smaller features are still being etched.
At Unaxis USA, we have developed a proprietary technique to eliminate the notch formation while maintaining high etch rate. This technique is integrated into time division multiplexed (TDM) Si etch processes, and is implemented in a single etch process. The conventional "bulk" etch to "finish" etch transition is thus made unnecessary, with the benefit of no end point detection and smooth and uniform etch profile. Etch processes are characterized and notch performance is measured as a function over etch percentage and feature aspect ratio. Using the new SOI etching technique, notching is completely eliminated in aspect ratios up to 9:1 and reduced to well below 100 nm for aspect ratios up to 18:1. Moreover, this new technique has been demonstrated to limit the effect of extensive overetch in increasing notch size.
Time division multiplexed (TDM) plasma etch processes have been widely applied to MEMS device manufacturing due to the capability of defining high aspect ratio features at high etch rates and mask selectivity. To etch anisotropic features using F-based chemistry, a TDM process cyclically alternates between etch and passivation steps, which are normally carried out with different gases introduced into a reaction chamber at different flow rates, and during which chamber pressures are maintained at different levels. Conventional process control methods often result in chamber pressure overshoot and/or undershoot, slow pressure response times, and long-term pressure drifts. These are undesirable effects in manufacturing MEMS devices due to the requirements on process stability, reliability and
repeatability.
At Unaxis USA Inc., a proprietary control technique has been developed for the TDM etch processes to better control chamber pressures and improve process stability. Controls over the movement of a throttle valve are realized through a combination of pre-positioning the valve and regulating it with the proportional, integral and derivative (PID) function mechanisms. Using this technique, we have demonstrated in fast TDM processes that pressure overshoot and undershoot are significantly suppressed, pressure response times are improved, and long-term pressure drifts are
eliminated. To this end, this new control technique has been successfully tested in processes where the etch/passivation process steps are alternating at frequencies up to 1 Hz. Applications of this advanced technique in deep silicon etching have demonstrated improved etch performance. As a result, this advanced pressure control
technique enables the TDM dry etching technologies for MEMS devices manufacturing to become markedly more reliable and stable.
KEYWORDS: Etching, Silicon, Switching, Time division multiplexing, Microelectromechanical systems, Plasma, Microsoft Foundation Class Library, Manufacturing, Plasma etching, Polymers
Sidewall smoothness is often a critical requirement for many MEMS devices, such as microfludic devices, chemical, biological and optical transducers, while fast silicon etch rate is another. For such applications, the time division multiplex (TDM) etch processes, so-called "Bosch" processes are widely employed. However, in the conventional TDM processes, rough sidewalls result due to scallop formation. To date, the amplitude of the scalloping has been directly linked to the silicon etch rate.
At Unaxis USA Inc., we have developed a proprietary fast gas switching technique that is effective for scalloping minimization in deep silicon etching processes. In this technique, process cycle times can be reduced from several seconds to as little as a fraction of second. Scallop amplitudes can be reduced with shorter process cycles. More importantly, as the scallop amplitude is progressively reduced, the silicon etch rate can be maintained relatively constant at high values. An optimized experiment has shown that at etch rate in excess of 7 μm/min, scallops with length of 116 nm and depth of 35 nm were obtained. The fast gas switching approach offers an ideal manufacturing solution for MEMS applications where extremely smooth sidewall and fast etch rate are crucial.
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