Lithography simulation is an essential technique for today's semiconductor manufacturing process. Although several rigorous models have been proposed, these methods are time-consuming. In order to calculate a full chip in realistic time, a fast and accurate resist model is essential. This paper proposes a new compact resist model using an arbitrary convolution kernel. The convolution formula can be described as a system of linear equations, therefore, we can determine the convolution kernel by solving the system of linear equations. However, it is hard to find the effective solution, because it is an ill-posed linear inverse problem due to the measurement constraints. Therefore, the key point of our method is how to solve the ill-posed linear inverse problem. In this paper, we explain the details and effectiveness of our method.
Lithography hotspot detection using lithography simulation (LCC) in a design stage is one of important techniques in order to avoid yield loss caused by the hotspots. Conventional LCC should detect all hotspots observed on wafer and reduce false errors which are not hotspots on wafer. However, the conventional LCC is not enough to meet the requirement. In this paper, we propose a multi-criteria hotspot detection method with a pattern classification technique. The proposed method uses a peak intensity value as the criterion and different criteria are used for different pattern categories. The categories are created based on K-means algorithm. Experimental results show our proposed method can reduce a number of false errors by 75% without any overlooking of hotspots.
Lithography hotspot detection and correction in the layout design phase is important to suppress manufacturing yield loss. Although machine learning based hotspot detection methods are considered as effective solutions over conventional lithography simulation, it is still difficult to apply them to practical layout design tasks because of a trade-off between detection accuracy and false alarms. In this paper, we propose a fast, accurate and reliable method to detect lithography hotspot candidates based on coherence map. Experimental results show that our method outperforms typical machine learning based hotspot detection models on industrial benchmark.
Lithography simulation is an essential technique for today’s semiconductor manufacturing process. In order to calculate an entire chip in realistic time, compact resist model is commonly used. The model is established for faster calculation. To have accurate compact resist model, it is necessary to fix a complicated non-linear model function. However, it is difficult to decide an appropriate function manually because there are many options. This paper proposes a new compact resist model using CNN (Convolutional Neural Networks) which is one of deep learning techniques. CNN model makes it possible to determine an appropriate model function and achieve accurate simulation. Experimental results show CNN model can reduce CD prediction errors by 70% compared with the conventional model.
Lithography simulation is an essential technique for today's semiconductor manufacturing process. In order to calculate an entire chip in realistic time, compact resist model is commonly used. The model is established for faster calculation. To have accurate compact resist model, it is necessary to fix a complicated non-linear model function. However, it is difficult to decide an appropriate function manually because there are many options. This paper proposes a new compact resist model using CNN (Convolutional Neural Networks) which is one of deep learning techniques. CNN model makes it possible to determine an appropriate model function and achieve accurate simulation. Experimental results show CNN model can reduce CD prediction errors by 70% compared with the conventional model.
As technology node shrinks down, hotspots, i.e. patterning failures on wafer after etching process, become an inevitable
problem. The main cause of such hotspots is low contrast of aerial image. There are several methods that can improve
aerial image contrast such as SRAF insertion and OPC. However, it is difficult to fix all hotspots by applying only SRAF
and OPC in advanced technology node. This paper proposes a new post-layout optimization method, before SRAF and
OPC, based on SOCS kernel for improving aerial image contrast and reducing hotspots. Experimental results show average
4nm PV-band improvement, as a result of contrast improvement.
KEYWORDS: Lithography, Computer simulations, 193nm lithography, Feature extraction, Simulation of CCA and DLA aggregates, Semiconducting wafers, Manufacturing, Etching, Scanning electron microscopy, Photomasks
As minimum feature sizes shrink, unexpected hotspots appear on wafers. Therefore, it is important to detect and fix these hotspots at design stage to reduce development time and manufacturing cost. Currently, as the most accurate approach, lithography simulation is widely used to detect such hotspots. However, it is known to be time-consuming. This paper proposes a novel aerial image synthesizing method using regression and minimum lithography simulation for only hotspot detection. Experimental results show hotspot detection on the proposed method is equivalent compared with the results on the conventional hotspot detection method which uses only lithography simulation with much less computational cost.
A resist cross-sectional profile becomes worse as feature sizes shrink. The bad resist profile could result in a hotspot after etching process (after-etch hotspot). Conventional simulation method is difficult to detect such hotspots accurately because it does not consider process variation. In this paper, we propose an accurate after-etch hotspot detection methodology with consideration of process variation based on optical intensity and defect rate. An experimental result shows our method can detect an after-etch hotspot accurately.
A new optical metric, termed resist deformation factor (RDF), to represent deformation of three-dimensional (3D) resist profile has been introduced into a source and mask optimization (SMO) flow to mitigate defects caused by a reactive ion etching (RIE) process at the lithography stage. Under the low-k1 lithography conditions with both a highly-coherent source and a complicated mask, the 3D resist profile is subject to top-loss or bottom footing, resulting in hotspots and/or defects after the RIE process. In order to represent the 3D resist profile on a fast lithography simulation, a sliced latent image along resist depth direction is used to define RDF as the ratio of integrated optical intensities within the resist pattern to those around its surrounding area. Then the SMO flow incorporating the RDF into its cost function is implemented to determine both a source and a mask as the 3D resist profile is less likely to deform. The result of new SMO flow with RDF shows 30% improvement of resist top-loss.
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