KEYWORDS: Field programmable gate arrays, Logic, System on a chip, Signal processing, Remote sensing, Satellites, Computer architecture, Data processing, Prototyping, Aerospace engineering
Systems on Chip (SoC) are present in a wide range of applications. This diversity in addition with the quantity of critical
variables involved in their design process becomes it as a great challenging topic. FPGAs have consolidated as a
preferred device to develop and prototype SoCs, and consequently Partial Reconfiguration (PR) has gained importance
in this approach. Through PR it is possible to have a section of the FPGA operating, while other section is disabled and
partially reconfigured to provide new functionality. In this way hardware resources can be time-multiplexed and
therefore it is possible to reduce size, cost and power. In this case we focus on the implementation of a SoC, in an
FPGA-based board, with one of its peripherals being a reconfigurable partition (RP). Inside this RP different hardware
modules defined as reconfigurable modules (RM) can be configured. Thus, the system is suitable to have different
hardware configurations depending on the application needs and FPGA limitations, while the rest of the system
continues working. To this end a MicroBlaze soft-core processor is used in the system design and a Virtex-5 FPGA
board is utilized to its implementations. A remote sensing application is used to explore the capabilities of this approach.
Identifying the section(s) of the application suitable of being time-shared it is possible to define the RMs to place inside
the RP. Different configurations were carried out and measurements of area were taken. Preliminary results of the
performance-area utilisation are presented to validate the improvement in flexibility and resource usage.
KEYWORDS: Signal processing, Global Positioning System, Clocks, Parallel computing, Remote sensing, Data storage, Computer architecture, Satellites, Receivers, Data processing
The increasing campaigns of GNSS-R scenario have put great pressure on high performance post-processing
design into the space level instrumentation. Due to large scale of information acquisition and the intensive
computation of cross-correlation waveform (CC-WAV), the overhead between the processing time and the storage
of amount of data prior to downlink issues has lead us to get the solution of real-time parallel processing design on
board. In this paper, we focus on the interaction of the chip level multiprocessing architecture and applications,
which show that the unbalanced workload of the transmission and processing can be compensated on the novel
architecture, Heterogeneous Transmission and Parallel Computing Platform (HTPCP). The intention of HTPCP
is to get a solution for the bus congestion and memory allocation issues. The pros and cons of SMP and HTPCP
are discussed, and the simulation results prove that HTPCP can highly improve the throughput of the GOLD-RTR
system.
The remote sensing techniques have put great pressure on real-time waveform post-processing design. Due to the
intensive computation and multi-channel waveform integration, the overhead between the processing time and the
storage of amount of data prior to downlink issues has lead us to get the solution of task-level parallelism. With the
development of IC design and innovation of architecture, embedded system can range from a single microprocessor to a
complex multi-processor and even including the embedded operating system (OS) on a chip. Therefore symmetric
multiprocessing (SMP) with embedded OS offers an attractive way to expose coarse-grained parallelism application.
In this paper we demonstrate a new modeling approach. In order to simplify the system; a workload model is derived
from a remote sensing application, which represents the workload characteristic and time degrading factors. The
intention is to leverage the task-level parallelism load is evenly to each processor in SMP, with the OS level testing to
speculate the bottleneck in hardware level. This parallel workload model which maps to a 6-LEON3 SMP architecture,
attains a 2.7x mean speedup over a single-LEON3 baseline; with 3-LEON3 attains a 2.23x mean speedup; with 2-
LEON3 attains a 1.78x mean speedup over a single-LEON3 baseline. Due to the involved sharing resources and
scheduling of multiple CPUs, the system will have a degrading in processing speed. With this lag we could infer the
hardware pipeline efficiency. And afford on the processor-set subsystem and memory subsystem analysis reveal the
affects on the system throughput.
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