Paper
13 June 2024 CFPara: a combination of coarse and fine-grained FPGA parallel routing methods
Yiwen Li
Author Affiliations +
Proceedings Volume 13180, International Conference on Image, Signal Processing, and Pattern Recognition (ISPP 2024); 131801Y (2024) https://doi.org/10.1117/12.3033797
Event: International Conference on Image, Signal Processing, and Pattern Recognition (ISPP 2024), 2024, Guangzhou, China
Abstract
FPGA is an emerging hardware productivity that is characterized by high flexibility, reconfigurability and moderate cost. The development of FPGA EDA software is relatively lagging behind due to the problems of difficult programming and excessive compilation time, which constrains the upward expansion of the FPGA field. In this paper, we aim to solve the problem of long compilation time of FPGA EDA software, and make an in-depth study on routing, which is one of the most time-consuming steps in the compilation process. A combination of coarse- and fine-grained FPGA parallel routing algorithm is proposed. Coarse-grained routing uses a load-balanced space partitioning strategy to generate a routing sequence tree, and when routing each net mesh, it switches to a fine-grained parallel algorithm to perform parallel routing within the net mesh with one source-sink node pair. Experiments show that the CFPara algorithm proposed in this paper compared to the VPR PathFinder algorithm can obtain a 11.7× speedup ratio.
(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.
Yiwen Li "CFPara: a combination of coarse and fine-grained FPGA parallel routing methods", Proc. SPIE 13180, International Conference on Image, Signal Processing, and Pattern Recognition (ISPP 2024), 131801Y (13 June 2024); https://doi.org/10.1117/12.3033797
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Field programmable gate arrays

Detection and tracking algorithms

Multiplexing

Electronic design automation

Computer hardware

Computer programming

Industry

RELATED CONTENT

Embedded systems for controlling LED matrix displays
Proceedings of SPIE (December 14 2016)
RPython high-level synthesis
Proceedings of SPIE (September 28 2016)
Comparison of modular multipliers on FPGAs
Proceedings of SPIE (December 24 2003)
Design flow for the reconfigurable HW platform XPP
Proceedings of SPIE (July 02 2002)
An FPGA routing algorithm to improve efficiency and quality
Proceedings of SPIE (October 10 2023)

Back to Top