Photonic integrated circuits provide a scalable platform for photonics-based quantum technologies. However, integrating quantum emitters and electro-optic cavities within this platform remains an open challenge proving to be a major hurdle from implementing key functionalities for quantum photonics, such as single photon sources and nonlinearities. Here, we address this shortcoming with the hybrid integration of InAs/InP quantum dot emitters on foundry silicon photonics and the implementation of photonic crystal cavities in thin-film lithium niobate. Co-integrated on-chip electronics allow us to tune the emission properties of the quantum dots while enabling GHz-rate coherent modulation over photons trapped in the cavities, thus providing a new level of programmability over interactions between optical fields and atom-like systems in integrated circuits. Our results open the door to a new generation of quantum information processors that can be manufactured in leading semiconductor foundries.
Thin Film Lithium Niobate (TFLN) photonic integrated circuits offer several improvements over other platforms in terms of material loss, energy efficiency, and operational bandwidth. We review our recent demonstration of quadrature phase shift keying in an ultrasmall TFLN photonic crystal-based IQ modulator. Our modulator features a footprint of 40 × 200 μm2 along with quality factors approaching 105 providing it with a Vπ = 1.16 V [H. Larocque et al. CLEO 2023, paper STh1R.3; H. Larocque et al. arXiv:2312.16746]. We discuss an extension to and optimization of quadrature amplitude modulation encoding schemes tailored to the device’s voltage response, including the use of a deep neural network for streamlining bit error rate minimization.
Existing photonic matrix processers are too small to tackle relevant problems. Here, I review our group’s recent work on scaling up analog photonic platforms. This work includes iterative advances to old approaches (accurate methods to calibrate MZI meshes), experimental demonstrations of recent proposals (a VCSEL array-based coherent detection ONN and a single-shot ONN based on reconfigurable free-space optical fan-out and weighting), and entirely new architectures (WDM-powered and RF-photonic fiber circuits for edge computing). The lessons learned from studying this diverse array of approaches helps inform the future development of photonic hardware for computation.
We demonstrated a large-scale space-time-multiplexed homodyne optical neural network (ONN) using arrays of high-speed (GHz) vertical-cavity surface-emitting lasers (VCSELs). Injection locking enables precise phase control over tens of VCSEL devices simultaneously, facilitating photoelectric-multiplication-based matrix operations and all-optical nonlinearity, operating at the quantum-noise limit. Our VCSEL transmitters exhibit ultra-high electro-optic conversion efficiency (Vπ=4 mV), allowing neural encoding at 5 attojoule/symbol. Three-dimensional neural connectivity allows parallel computing. The full-system energy efficiency reaches 7 fJ/operation, which is >100-fold better than the state-of-the-art digital microprocessors and other ONN demonstrations. Digit classification is achieved with an accuracy of 98% of the group truth.
Subwavelength grating (SWG) metamaterial structures are excellent platforms for guided-wave nonlinear optics, but their design and optimization are challenging due to the large number of geometric degrees of freedom and the need for compute-intensive 3D simulations. Here, we demonstrate inverse design of χ(2) SWG waveguides using an efficient and accurate differentiable plane-wave expansion (PWE) eigensolver. Our solver, which incorporates sparse iterative algorithms and subpixel smoothing, enables efficient eigensolution and end-to-end differentiation from geometric parameters to the SWG figure of merit, which depends both on the eigenvalues (first-order perturbation theory) and the eigenvectors and group indices (second-order perturbation theory), both in forward- and reverse-mode. We apply this solver to the design and optimization of metamaterial waveguides for two types of backward SHG: idler-reversed and pump-reversed. This approach may find use in designing periodic structures more generally, including nanobeam cavities, slow-light modulators, and vertically coupled resonators.
Conventional multiport interferometers based on MZI meshes suffer from component imperfections, which limit their scaling. We introduce two new designs that overcome this limitation: a 3-splitter MZI for generic errors and a broadband MZI+Crossing design for more realistic correlated errors. These architectures, motivated by the correspondence between SU(2) and the Riemann sphere, are more error tolerant than the standard MZI mesh and support progressive self-configuration. Numerical simulations reveal orders-of-magnitude error reductions compared to the standard MZI mesh; moreover, the mesh is asymptotically perfect: the matrix error decreases with mesh size.
KEYWORDS: Wavelength division multiplexing, Neural networks, Integrated optics, Modulators, Computer programming, Modulation, Analog electronics, Time-frequency analysis, Signal to noise ratio
We introduce an optical neural-network architecture for edge computing that takes advantage of wavelength multiplexing, high-bandwidth modulation, and integration detection. Our protocol consists of a server and a client, which divide the task of neural-network inference into two steps: (1) a difficult step of optical weight distribution, performed at the server and (2) an easy step of modulation and integration detection, performed at the edge device. This arrangement allows for large-scale neural networks to be run on low-power edge devices accessible by an optical link. We perform simulations to estimate the speed and energy limits of this scheme.
Optical approaches to machine learning rely heavily on programmable linear photonic circuits. Since the performance and energy efficiency scale with size, a major challenge is overcoming scaling roadblocks to the photonic technology. Recently, we proposed an optical neural network architecture based on coherent detection. This architecture has several scaling advantages over competing approaches, including linear (rather than quadratic) chip-area scaling and constant circuit depth. We review the fundamental and technological limits to the energy consumption in this architecture, which shed light on the quantum limits to analog computing, which are distinct from the thermodynamic (e.g. Landauer) limits to digital computing. Lastly, we highlight a recent "digital" implementation of our architecture, which sheds light on the scaling challenges associated with controlling aberrations in the free-space optical propagation.
Storing, processing, and learning from data is a central task in both industrial practice and modern science. Recent advances in modern statistical learning, particularly Deep Neural Networks (DNNs), have given record breaking performance on tasks in game playing,1, 2 natural language processing,3 computer vision,4 computational biology,5, 6 and many others. The rapid growth of the field has been driven by an increase in the amount of public datasets,7 improvements to algorithms,8 and a substantial growth in computing power.9 In order to perform well on these tasks networks have had to grow in size, learning more complicated statistical features. The training and deployment of these large neural networks has spurred the creation of many neural network accelerators to aid in the computation of these networks.10-12
Existing general purpose computing devices such as CPUs and GPUs are limited both by thermal dissipation per unit area and yield associated with large chips.13, 14 The design of Application Specific Integrated circuits (ASICs) has aided in decreasing the energy consumption per workload substantially by limiting the supported operations on chip. An example of this is the first generation tensor processing unit (TPU)15 which is able to perform the inference of large convolutional neural networks in datacenter in <10ms with an idle power of 28W and an workload power of 40W. It may seen counterintuitive then that the limiting factor for the implementation of DNNs is not computation, but rather the energy and bandwidth associated with reading and writing data from memory as well as the energy cost of moving data inside of the ASIC.15, 16 Several emerging technologies, such as in-memory computing,17 memristive crossbar arrays18 promise increased performance, but these emerging architectures suffer from calibration issues and limited accuracy.19
Photonics as a field has had tremendous success in improving the energy efficiency of data interconnects.20 This has motivated the creation of optical neural networks (ONNs) based on 3D-printed diffractive elements,21 spiking neural networks utilizing ring-resonators,22 reservoir computing23 and nanophotonic circuits.24 However, these architectures have several issues. 3D-printed diffractive networks and schemes requiring spatial light modulators are non-programmable, meaning that they are unable to perform the task of training. Nanophotonic circuits allow for an O(N2) array of interferometers to be programmed, providing passive matrix-vector multiplication. However, the large (≈1mm2) size of on chip electro-optic interferometers means that scaling to an array of 100x100 would require 10; 000mm2 of silicon, demonstrating the limitations of scaling this architecture. To date no architecture has demonstrated high-speed (GHz) speed computation with more than N ≥ 10; 000 neurons.
Here we present an architecture that is scalable to N ≥ 106 neurons. The key mechanism of this architecture is balanced homodyne detection. By scaling the architecture to such a large size we show that we can decimate energy costs per operation associated with the optical component of this architecture, reaching a bound set by shot noise on the receiving photodetectors which leads to classification error. We call this bound a standard quantum limit (SQL) which reaches 100zJ/MAC on problems such as MNIST. We also analyze the energy consumption using existing technologies and show that sub-fJ/MAC energy consumption should be possible.
This paper is organized as follows: In section 1 we will discuss the function of this architecture as a matrixmatrix processor. In section 2 we will analyze the energy consumption of the architecture. In section 3 we will discuss methods for training and extending the accelerator to a broader scope of problems, namely convolutionally neural networks (CNNs).
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