Transistor architectures below the 7 nm node are significantly enabled by EUV lithography, with single exposure EUV processes simplifying small pitch patterning processes. However, EUV stochastics are a significant hurdle in meeting aggressive process assumption targets and achieving high yields. In particular, line edge roughness and line width roughness (LER and LWR) at EUV patterned gate have been identified as key limiters of device performance and yield within these nodes. Here, we study the impact of different illumination schemes on gate LER and LWR. We specifically utilize NILS to target LER and LWR reduction, with high NILS observed to primarily reduce high frequency roughness. Post etch, a largely illumination independent reduction in the mid and high frequency regimes is observed. Finally, impact of illumination on long channel gate patterning is assessed and a NILS independent LWR response is observed both post development and etch.
IBM Research recently announced that 2nm node Nanosheet Technology is able to deliver superior density, power and performance compared to today’s 7nm FinFET technology in mass production. To enable 2nm node Nanosheet Technology, advanced patterning solutions are required. Dimensional compression drives the need for advanced patterning solutions including wider use of extreme ultraviolet (EUV) lithography. This also creates higher in feature aspect ratios, which in turn creates additional challenges during plasma etch. As aspect ratios continue to increase, difficulty with in-feature ion, radical, and volatile species transport during plasma etch presents an exceptional challenge. Dimensional scaling and wider use of EUV increases the need for further reduction of critical dimension (CD) variability, including line edge and line width roughness. The introduction of 3-dimensional gate all around nanosheet architecture has introduced an additional unique set of patterning challenges to address for coming technology nodes. When combined with dimensional scaling there is a clear need for novel advanced patterning process solutions to enable future nodes. In this presentation a variety of these challenges and the impact they will have on device and node scaling will be introduced and reviewed.
As contact dimensions continue to shrink to support scaling, local CD variation (LCDU) becomes a critical driver of electrical variation and defectivity. Continued logic scaling is highly dependent on middle of line (MOL), which further amplifies the need for LCDU improvement. LCDU improvement will be critical to improving edge placement error (EPE). The same concepts can also be applied to back end of line (BEOL) vias. Since lithography tools are unable to consistently print contacts below 20 nm, it is typically necessary to shrink through etch. There are various etch techniques we can use to shrink contact dimensions each having different impacts on LCDU and defectivity. In this study we explore the impacts of various shrink methods to optimize LCDU and defect density. In this study a simple patterning stack of SiN + OPL + ARC + resist is used to simulate contact patterning. Various etch chambers and shrink techniques are used to reach a target CD range and LCDU and defect density are evaluated. The chambers evaluated include TEL’s conductor etcher and TEL’s dielectric etcher. LCDU data is collected using CDSEM. Defect density is evaluated using various etch techniques. Etch techniques such as deposition on resist, ARC and OPL, descum steps, pulsing and quasi atomic layer etch are explored. Multiple types of deposition techniques are used including selective deposition and cyclic deposition and trim. These techniques are optimized to be sensitive to open area and correct for local CD variations. On wafer LCDU performance of <2.0nm is demonstrated and further optimization is done to minimize defectivity.
The ability to etch silicon highly anistropically at active fin heights of 45nm or greater is critical to fin patterning for continued CMOS scaling. Tight control of fin CD and taper is critical toward controlling the device, with particular importance to channel control. In this study we explore the quasi-atomic layer etch (qALE) parameter space in order to better understand the impact of plasma conditions on fin CD, profile, and aspect ratio dependent etch phenomena. A qALE solution is needed to provide a manufacturable solution for a vertical square bottom fin.
In this study a cyclic chlorination (surface modification) + ion bombardment process (modified surface removal) is used to etch Si with a Si3N4 hard mask. Various parameters are explored including bias power, pressure, and time in the ion bombardment step as well as source power, pressure, and time in the chlorination step. With regards to the ion bombardment step, varying time helps to quantify the self-limitation of the etch process, modulating pressure helps to quantify the impact of reduced mean free path and ion density, and modifying source power helps to quantify the impact of changes to ion density. For the chlorination step, varying time helps to quantify the self-limitation of surface modification mechanism, and modifying source power illustrates the impact of Cl radical density on surface modification. These various mechanisms will be explored with the particular view point of how these changes can impact ultimate channel performance.
Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet technology in the FEOL. While sheet and gate pitches expected for the beyond 7nm node fall within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet device performance requirements at technology critical sheet widths and gate lengths. Here, we demonstrate electrical performance of nanosheet FET’s with 20 – 80 nm wide sheets with 40-150 nm pitch gates patterned with single expose EUV. We compare results against a benchmark double patterning process towards meeting variability, device and critical dimension targets. We also explore the limits of process and material knobs - resists, illuminations and etch chemistries with the specific goal of reducing LER/LWR and towards shrink for further scaling. Our results demonstrate crossover points between direct print EUV and double patterning processes for nanosheet technology and identify relevant design guidelines and focus areas to successfully enable EUV for the FEOL in nanosheets.
Background: With aggressive scaling of single-expose (SE) extreme ultraviolet (EUV) lithography to the sub-7-nm node, stochastic variations play a prominent role in defining the lithographic process window (PW). Fluctuations in photon shot noise, absorption, and subsequent chemical reactions can lead to stochastic failure, directly impacting electrical yield.
Aim: Fundamental characterization of the mode and magnitude of these variations is required to define the threshold for failure.
Approach: A complementary series of techniques is enlisted to probe the nature and modulation of stochastic variation in SE EUV patterning. Unbiased line edge roughness (LER), local critical dimension uniformity (LCDU), and defect inspection techniques are employed to monitor the frequency of stochastic variations leading to failures in line/space (L/S) and via patterning.
Results: When characterizing different resists and illumination conditions, there is no change in unbiased LER or via LCDU with increasing critical dimension (CD). Stochastic defect density is correlated with CD for both L/S and via arrays, and there is a strong correlation with L/S electrical yield data.
Conclusions: Traditional 3σ LER and via LCDU measurements are not sensitive enough to define and improve PW. For PW centering and yield improvement, stochastic defect inspection is a necessity.
A methodology of obtaining the local critical dimension uniformity of contact hole arrays by using optical scatterometry in conjunction with machine learning algorithms is presented and discussed. Staggered contact hole arrays at 44 nm pitch were created by EUV lithography using three different positive-tone chemically amplified resists. To introduce local critical dimension uniformity variations different exposure conditions for dose and focus were used. Optical scatterometry spectra were acquired post development as well as post etch into a SiN layer. Reference data for the machine learning algorithm were collected by critical dimension scanning electron microscopy (CDSEM). The machine learning algorithm was then trained using the optical spectra and the corresponding calculated LCDU values from CDSEM image analyses. It was found that LCDU and CD can be accurately measured with the proposed methodology both post lithography and post etch. Additionally, since the collection of optical spectra post development is non-destructive, same area measurements are possible to single out etch improvements. This optical metrology technique can be readily implemented inline and significantly improves the throughput compared to currently used electron beam measurements.
Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet patterning as a replacement to complex double patterning schemes. While front-up sheet pitches and gate pitches expected for the beyond 7nm node fall well within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet variation requirements at technology minimum sheet widths and gate lengths. Here, we explore the crossover point between direct print EUV and optical/EUV based double patterning processes for sheets and gates in the 40 – 50 nm sheet pitch/CPP regime. We demonstrate that to enable the minimum sheet widths of <20nm required for the technology, direct bright field print with shrink results in high variability. We develop a tone invert process with darkfield sheet print that utilizes a polymerizing etch to reduce variability and achieve sub-20nm sheet widths with reduced variability, comparable to a self-aligned double patterning (SADP) process. With gate length variation requirements being tighter, we show that SADP still yields a considerable improvement in line edge/width roughness over a direct print process. We project EUV technology into the future to quantify improvements that would enable direct printed gates that match SADP. Our results will provide a guideline to down-select patterning processes for the nanosheet front end while optimizing cost and complexity.
With aggressive scaling of single-expose EUV lithography to the sub-7 nm node, stochastic variations play a prominent role in defining the lithographic process window. Fluctuations in photon shot noise, absorption and subsequent chemical reactions can lead to stochastic failure, directly impacting electrical yield. Fundamental characterization of the mode and magnitude of these variations is required to define the threshold for failure. In this work, a complementary series of techniques is enlisted to probe the nature and modulation of stochastic variation in single exposure EUV patterning. Unbiased line edge roughness (LER), local critical dimension uniformity (LCDU) and defect inspection techniques are employed to monitor the frequency of stochastic variations leading to failures in line/space and via patterning. Using this methodology, we explore the modulation of stochastic variations by different photoresists and illuminations, with emphasis on material and process down-selection for improved yield at the sub-7 nm node.
Self-Aligned Quadruple Patterning (SAQP) is a promising technique extending the 193-nm lithography to manufacture structures that are 20nm half pitch or smaller. This process adopts multiple sidewall spacer image transfers to split a rather relaxed design into a quarter of its original pitch. Due to the number of multiple process steps required for the pitch splitting in SAQP, the process error propagates through each deposition and etch, and accumulates at the final step into structure variations, such as pitch walk and poor critical dimension uniformity (CDU). They can further affect the downstream processes and lower the yield. The impact of this error propagation becomes significant for advanced technology nodes when the process specifications of device design CD requirements are at nanometer scale. Therefore, semiconductor manufacturing demands strict in-line process control to ensure a high process yield and improved performance, which must rely on precise measurements to enable corrective actions and quick decision making for process development. This work aims to provide a comprehensive metrology solution for SAQP.
During SAQP process development, the challenges in conventional in-line metrology techniques start to surface. For instance, critical-dimension scanning electron microscopy (CDSEM) is commonly the first choice for CD and pitch variation control. However, it is found that the high aspect ratio at mandrel level processes and the trench variations after etch prevent the tool from extracting the true bottom edges of the structure in order to report the position shift. On the other hand, while the complex shape and variations can be captured with scatterometry, or optical CD (OCD), the asymmetric features, such as pitch walk, show low sensitivity with strong correlations in scatterometry. X-ray diffraction (XRD) is known to provide useful direct measurements of the pitch walk in crystalline arrays, yet the data analysis is influenced by the incoming geometry and must be used carefully.
A successful implementation of SAQP process control for yield improvement requires the metrology issues to be addressed. By optimizing the measurement parameters and beam configurations, CDSEM measurements distinguish each of the spaces corresponding to the upstream mandrel processes and report their CDs separately to feed back to the process team for the next development cycle. We also utilize the unique capability in scatterometry to measure the structure details in-line and implement a “predictive” process control, which shows a good correlation between the “predictive” measurement and the cross-sections from our design of experiments (DOE). The ability to measure the pitch walk in scatterometry was also demonstrated. This work also explored the frontier of in-line XRD capability by enabling an automatic RSM fitting on tool to output pitch walk values. With these advances in metrology development, we are able to demonstrate the impacts of in-line monitoring in the SAQP process, to shorten the patterning development learning cycle to improve the yield.
The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.
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