Mr. Kaiping Liu Profile

Kaiping Liu

at Texas Instruments Inc

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Proceedings Article | 12 July 2002 Paper

Improving device performance and process manufacturability through the use of TCAD

Kaiping Liu, Jeff Wu, Jihong Chen, Amitabh Jain, Manoj Mehrotra

Proceedings Volume 4692, (2002) https://doi.org/10.1117/12.475676

KEYWORDS: Diffusion, Monte Carlo methods, TCAD, Dielectrics, Fluorine, Interfaces, Boron, Silicon, Transistors, Germanium

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The use of TCAD as a powerful tool for improving device performance and process manufacturability is describe din this paper. The ability for TCAD simulation to provide quick insight and understanding to better pMOS heavy doped drain extension design is illustrated. The impact of surface dielectric property and interface condition on the HDD diffusion profile, the transistor performance, and the transistor parametric variation is discussed through the use of SIMS profiles, simulation results, and silicon dat. Significant changes in HDD profile, transistor characteristics and parametric variability are attributed to surface oriented dopant diffusion. The severity of such changes can vary with varying surface dielectric properties. Through TCAD simulations, we postulate that the surface oriented dopant diffusion is mainly due to the existence of a super steep interstitial gradient (SSIG), in addition to SPE dopant transport effects. Monte Carlo implant simulations using UT-Marlowe and SIMS profiles how that higher-energy-lower-dose HDD implant would produce a better HDD diffusion profile of same junction depth than lower- energy-higher-dose HDD implant does, as a result of SSIG. SIMS experiments designed to reduce surface oriented diffusion by using Ge and F co-implant are discussed. The SIMS profiles show that Ge is able to reduce surface oriented dopant diffusion by steric effects, but F co- implant produces the best HDD profile.

Proceedings Article | 11 August 1999 Paper

Comparing the electrical characteristics and reliabilities of BJTs and MOSFETs between Pt and Ti contact silicide processes

Kaiping Liu, Ling Shang

Proceedings Volume 3883, (1999) https://doi.org/10.1117/12.360583

KEYWORDS: Titanium, Hydrogen, Platinum, Interfaces, Semiconducting wafers, Boron, Oxides, Transistors, Silicon, Resistance

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The sub-threshold characteristics and the reliability of BJTs, using platinum contact silicide (PtSi) or titanium contact silicide (TiSi₂), are compared and analyzed. During processing, it is observed that the TiSi₂ process produces higher interface state density (D_it) than the PtSi process. The increase in D_it not only leads to a higher base current in the BJTs, but also leads to a lower transconductance for the MOS transistors. The data also show that the impact on NPN and nMOS is more severe than the impact of PNP and pMOS, respectively. This can be explained by the non-symmetric interface state distribution, the re- activation of boron, and/or by substrate trap centers. The amount of interface states produced depends not only on the thickness of the titanium film deposited, but also on the temperature and duration of the titanium silicide process. The electrical data indicates that after all the Back-End- Of-The-Line processing steps, which includes a forming gas anneal, D_it is still higher on wafers with the TiSi₂ transistor's base current increases at different rates between the two processes, but eventually levels off to the same final value. However, the PNP transistor's base current increases at approximately the same rate, but eventually levels off at different final values. These indicate that the TiSi₂ process may have modified the silicon and oxygen dangling bond structure during its high temperature process in addition to removing the hydrogen from the passivated interface states.

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