Mitigating failures caused by electrostatic discharge (ESD) is a crucial problem in many applications of embedded systems. The paper analyses in a systematic way the propagation of ESD effects at structural and logical levels in order to find threats and capabilities of efficient system recovery. The presented considerations are illustrated with some results referred to commercially developed devices for registering and analyzing ECG signals.
In many applications microcontrollers run preemptive real-time operating systems and have to fulfill high reliability and performance requirements. Debugging and an evaluation of such systems require low-level access to the microcontroller state at every execution point. The modern MCU architectures contain special hardware modules, which generate the instruction trace and transmit it via specific physical interfaces. The execution traces provide accurate details of the program’s dynamic behavior. The trace information allows recreating the software context of the each executed instruction including instruction address, type of instruction, sometimes instruction arguments or the relevant branch target address. The collected data can be used for tracing the program control flow, verification of operating system operations or reliability metrics measurement (including code coverage or availability). The paper presents the original low-cost trace analyzing system for cortex-m microcontrollers. The author proposes a new methodology for the automatic trace collection during multiple test executions. The developed system provides several types of the program trace analysis. One of them is an anomaly detection of a firmware execution. The anomaly detection is based on a commonly known clustering algorithm with the distance metric designed by the author and the trace data preparation method. The usefulness of the system has been experimentally verified while testing an original embedded system.
In the paper we discuss the problem of evaluating disc performance with benchmarks. In particular, we concentrate on assessing benchmark properties. For this purpose we have developed benchmark managing platform which allows us to enhance the benchmark execution process with monitoring performance counters. The developed methodology and tool do not need additional benchmark instrumentation and have a negligible impact on its execution. The usefulness of this approach has been illustrated with experimental results covering a representative set of benchmark programs.
KEYWORDS: Error control coding, Tolerancing, Embedded systems, Resistance, General packet radio service, Telecommunications, Reliability, Detection and tracking algorithms, Sensors, Software development
This paper presents software methods of improving fault tolerance in embedded systems. These methods have been adapted to a telemetry system dedicated to tracking vehicles for logistics purposes. The developed telemetry system allows us to monitor vehicle position and some technical parameters via GSM communication. It comprises the capability of remote software reconfiguration. To evaluate dependability of the system we use a fault injection technique based on simulating bit-flip errors within memory cells. For this purpose an original testbed has been developed. It provides not only the capability of disturbing internal state of the tested system (via JTAG interface) but also the possibility of controlling system input states and observing its behavior (in particular output signals) according to specified test scenarios. The whole test process is automatized. The paper presents a case study related to a commercial product but the described methodology and techniques can be extended for other embedded systems.
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