We introduce a new algorithm (DFM Via Shift) to reposition vertical interconnect access (VIA) design patterns, considering the retargeted metal (both upper and lower layer) pattern, the user-defined max-shifting range, and the VIA design rule, for the purpose of achieving maximum metal coverage of VIAs. The DFM Via Shift algorithm considers VIAs that interact with each other based on spacing rules as a VIA cluster. All VIAs in a cluster are co-optimized, allowing for fully-covered VIAs with good positioning to be shifted to allow other, more critical VIAs to be optimized in some scenarios. We present the results of our research showing that the overall metal coverage of VIAs in 25nm node test chips can be significantly improved with repositioning. Nearly 95% of VIAs exposed out of metal after retargeting can be optimized to new, fully-covered positions in one of the test cases of the advanced node.
KEYWORDS: Design for manufacturing, Databases, Rule based systems, Semiconducting wafers, System identification, Visualization, Photomasks, Lutetium, Microelectronics, Design for manufacturability
In this paper we combined the hotspot pattern library and the rule-based scoring system into a modularized hotspot-checking rule deck running on an automatic flow. Several DFM (design for manufacture) properties criteria will be defined to build a “score board” for hotspot candidates. When hotspots in the input design are highlighted, the scoring system can identify whether a hotspot is a high risk hotspot or not, and define the severity of the hotspots by extracted DFM properties. The automatic flow will detect which layers are contained in the design then generate a modular rule deck with several corresponding hotspot check modules. The flow also takes snapshots of the high risk hotspots according to the score board automatically. After all the essential hotspot data is collected, the flow will automatically create an HTML-format report which has histograms of properties and overview graph that shows the distribution of hotspots. The aforementioned HTML report containing scored DFM properties and snapshots can help result-viewers to identify the high risk hotspots on the design quickly; namely, users can examine hotspots by snapshots without loading the whole design into layout viewer tools. By comparing the hotspot checking result with real defects from wafer data, a true hotspot’s values of DFM properties can be obtained. We believe this is helpful for users to improve their hotspot rules in accuracy.
The Mask Data Correctness Check (MDCC) is a reticle-level, multi-layer DRC-like check evolved from mask rule
check (MRC). The MDCC uses extended job deck (EJB) to achieve mask composition and to perform a detailed check
for positioning and integrity of each component of the reticle. Different design patterns on the mask will be mapped to
different layers. Therefore, users may be able to review the whole reticle and check the interactions between different
designs before the final mask pattern file is available. However, many types of MDCC check results, such as errors from
overlapping patterns usually have very large and complex-shaped highlighted areas covering the boundary of the design.
Users have to load the result OASIS file and overlap it to the original database that was assembled in MDCC process on
a layout viewer, then search for the details of the check results. We introduce a quick result-reviewing method based on
an html format report generated by Calibre® RVE. In the report generation process, we analyze and extract the essential
part of result OASIS file to a result database (RDB) file by standard verification rule format (SVRF) commands.
Calibre® RVE automatically loads the assembled reticle pattern and generates screen shots of these check results. All the
processes are automatically triggered just after the MDCC process finishes. Users just have to open the html report to
get the information they need: for example, check summary, captured images of results and their coordinates.
The mask composition checking flow is an evolution of the traditional mask rule check (MRC). In order to differentiate
the flow from MRC, we call it Mask Data Correctness Check (MDCC). The mask house does MRC only to identify
process limitations including writing, etching, metrology, etc. There still exist many potential errors that could occur
when the frame, main circuit and dummies all together form a whole reticle. The MDCC flow combines the design rule
check (DRC) and MRC concepts to adapt to the complex patterns in today’s wafer production technologies. Although
photomask data has unique characteristics, the MRC tool in Calibre® MDP can easily achieve mask composition by using
the Extended MEBES job deck (EJB) format. In EJB format, we can customize the combination of any input layers
in an IC design layout format, such as OASIS. Calibre MDP provides section-based processing for many standard verification
rule format (SVRF) commands that support DRC-like checks on mask data. Integrating DRC-like checking with
EJB for layer composition, we actually perform reticle-level DRC, which is the essence of MDCC. The flow also provides
an early review environment before the photomask pattern files are available. Furthermore, to incorporate the
MDCC in our production flow, runtime is one of the most important indexes we consider. When the MDCC is included
in the tape-out flow, the runtime impact is very limited. Calibre, with its multi-threaded processes and good scalability, is
the key to achieving acceptable runtime. In this paper, we present real case runtime data for 28nm and 14nm technology
nodes, and prove the practicability of placing MDCC into mass production.
Scatter Bar (SBAR) insertion is a computationally expensive operation. SBAR are usually generated rule-based. SBAR rule tables dictate the insertion of SBAR with different SBAR width dependent on the width of the printable main features and the spacing between the main features and SBAR. Optimization of the SBAR rules drives manufactures to ever more complex SBAR tables which increase the runtime. In advanced process nodes, SBAR printing issues, missing SBAR due to clean-up problems and joining SBAR of different width together remain challenging. On the other hand, pixelized inversion methods may yield optimized SBAR solutions, especially in terms of SBAR placement for contact layers, but comes at the expense of significant computational effort and increased mask writing and inspection time. Since OPC changes the spacing between SBAR and main features, an accurate and optimized SBAR solution requires OPC and SBAR optimization to run interactively.
This work focuses on both line/space and contact layers To ensure fast SBAR optimization, SBAR placement and SBAR width optimization are separated. SBAR of uniform width are placed fast driven by a simple rule-based table comprising only a single SBAR width. This intermediate SBAR layer is subject into a model-based approach, which fragments the SBAR layer based on proximity with respect to the main features or other SBAR, and assigns measurement sites to each SBAR fragment. A model is used to move each SBAR fragment inward or outward so that the image cut line shows a maximum SBAR intensity closer to a predefined SBAR printing threshold. While the main features are unchanged, several iterations are applied to converge the SBAR fragments. Keeping the SBAR fragments fixed, OPC is applied to the main features. Repeating these steps allows optimization of the SBAR width and the OPC simultaneously. Site based as well as contours based verification methods are applied to ensure that the SBAR printing margin has been significantly improved. The improved SBAR printing margin allows manufactures to apply more aggressive SBAR placement rules, which, in addition to the optimized SBAR width, helps to enlarge the depth of focus, therefore, widen the common process window of the lithography process.
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