L3Harris Technologies recently patented infrared detector arrays made by directly bonding a III-V Type II Superlattice (T2SL) detector to an optical silicon wafer. The process is performed at the wafer level and can replace L3Harris’ traditional adhesive bond. Direct bonding offers several advantages over adhesive bonding. First, higher operability and fewer defect clusters result due to the rigorous preparation of wafer surfaces before bonding. The number of antireflection coated surfaces is decreased from three to one. Higher quantum efficiency results from the improved transmission through the III-V/Si interface. This is critical for multi-band detectors, which operate over a relatively wide spectral bandwidth. Finally, the bond withstands higher processing temperatures than the adhesive bond. The process has been demonstrated on 150mm silicon with III-V wafers up to 125mm in diameter. The optical silicon remains in the finished focal plane array (FPA), serving as a protective window on the front surface of the delicate detector array. The silicon is a key component to L3Harris FPAs, forcing a coefficient of thermal expansion (CTE) match between the detector array and the silicon readout integrated circuit. The CTE match enables large array formats and long thermal cycle life without shimming.
L3Harris has developed a multispectral sensor architecture that opens doors to the incorporation of enabling functionality for future applications. This sensor architecture, while detector material agnostic in nature, builds upon our type-II superlattice (T2SL) technology, which was originally developed through the tri-service Vital Infrared Sensor Technology Acceleration (VISTA) program. The sensor architecture consists of stacked absorber layers that can be individually processed as they are integrated into the sensor stack. This layer-based approach enables the insertion of additional functional structures to enhance performance, such as embedded dielectric filters for efficient spectral separation, which would not be possible in a monolithic design. Due to the additional degrees of freedom with this configuration, it is necessary to design the filter such that it is compatible with the process required to functionalize each absorber while simultaneously meeting performance requirements. In this work, we report on various filter designs impacting the performance of focal plane arrays (FPAs) having embedded dielectric filters, under various practical constraints.
The tri-service Vital Infrared Sensor Technology Acceleration (VISTA) program rapidly matured III-V semiconductor epitaxy to produce tactically viable detectors using Type II Superlattice (T2SL) structures. The T2SL material system allows tunable band gaps for creating lattice-matched heterojunction devices. Heterojunction devices are integral to suppressing sources of dark currents, such as internal Shockley Reed Hall (SRH) and device surface currents. Once the VISTA program demonstrated that T2SL detectors offered competitive performance to traditional indium antimonide (InSb) detectors at an operating temperature 40K to 50 K higher, many opportunities emerged. This elevation in operating temperature provides two benefits to infrared (IR) sensors. The first is to miniaturize the integrated Dewar-electronicscooler assembly (IDECA) such that it can support small aerial vehicle and soldier mounted sensors. The second is to increase the mean time to failure (MTTF) of an existing InSb IDECA. To benefit from T2SL higher operating temperature (HOT) detectors, the overall cost of the IDECA must be competitive with InSb. This drives a manufacturing capability that is equivalent to InSb. At the L3 Space and Sensors Technology Center (L3 SSTC), the III-V detector foundry processes 125 mm diameter InSb wafers. The development of 125 mm diameter T2SL detector wafers started with the gallium antimonide substrates. The greater size and weight of these substrates required extra care to avoid breakage. Leveraging the learning reported from the silicon industry, we developed a specification for the substrate thickness and edge bevel to provide a robust platform for wafer processing. Next, we worked with commercial III-V epitaxy suppliers to develop multi-wafer growth capability for 125 mm diameter substrates. The results of this effort, funded by the Office of the Secretary of Defense (OSD) Defense-wide Manufacturing Science and Technology (DMST) program through the Army Night Vision and Electronic Sensor Directorate (NVESD), we were able to improve focal plane array (FPA) yield from virtually zero to InSb manufacturing levels.
The evolution of InSb Focal Plane Arrays (FPAs) at L-3 Communications Cincinnati Electronics (L-3 CE) has resulted in large format, high reliability, and high yields for 256x256, 640x512, 1Kx1K and even 2Kx2K formats using our patented front-side illuminated, reticulated pixel design. Baseline processes matured at 30um pitch and gradually were made producible at 25um pitch. Recent progress in process technology, specifically dry etch plasma processes and photolithography tools, has created a new set of processes/design capabilities which enable 15um pixel pitch FPAs, thus allowing us to develop a 15um pitch FPA with 4 times as many pixels, in the same foot print as the previous 30um pitch designs. We have developed a new 15um pitch, reticulated pixel design, implemented on a 512x512 format, which can then be sized into larger arrays, similar to the evolution that occurred on 30um pitch FPAs. As unit cell dimensions shrink by a factor of two, both the feature size and the alignment tolerances begin to limit optical fill factor. Addition of a novel micro-optic design, which optimizes signal collection to near 100% efficiency while maintaining near theoretical pixel MTF, will be presented.
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