Memory industry has been pursuing endless shrinking technology which increases fabrication complexity. It poses problems between adjacent layers as well as within a single layer. To verify the interlayer design, we have developed the interlayer design verification methodology using contour image. Our methodology makes it possible to verify interlayer design visually by extracting the contour image from the real patterns. And we can verify interlayer design even during the fabrication process and conduct a non-destructive inspection. Also this methodology provides a statistical analysis of massive measured data. Through this methodology, we can calculate the margin of current interlayer design and suggest the requirement of design.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.