Stochastic printing variations are a challenge for EUV lithography and it is well known that these variations worsen if exposed out-of-focus because the EUV image contrast degrades. The introduction of 0.55NA will improve image contrast at a reduced depth-of-focus. This paper will describe how best focus planes differences between features can be used to design focus-sensitive metrology targets that can report EUV focus if used in combination with an optical metrology tool. Moreover, the developed target methodology ensures design rules compliance. The focus metrology target concept is experimentally demonstrated using a 24nm pitch line/spacer in combination with a low-n EUV mask absorber material, metal-oxide-resist (MOR), and a 0.33NA EUV scanner. The observed focus variation is modeled to quantify how much content is correctable using scanner feedback. This illustrates that on-product focus metrology can improve focus performance if combined with advanced process control.
Scanners in High-Volume-Manufacturing conditions will experience a large range of reticles that vary in reticle transmission and reticle diffraction characteristics. Especially under full production loads reticles will heat up due to the exposure light-load and as such experience thermo-mechanical deformations. The resulting reticle pattern distortion can be partially translated in a deteriorated overall system overlay. Due to the geometry of the reticle and exposure fields, these reticle thermal effects are in general barrel-shape distortions that can be well corrected with the available set of lens manipulators. Nevertheless node-over-node the residual overlay errors associated with thermo-mechanical reticle deformation needs further reduction since it contributes to the total onproduct overlay performance. To reduce overlay caused by reticle temperature drift, NXT1980Di includes an active cooling mechanism suppressing the reticle temperature changes during exposure significantly. Even though the reticle temperature excursions are well suppressed, residual intra-wafer overlay drift effect can still be observed. Before exposure of a wafer, reticle deformation is measured during reticle align using in-line alignment / image sensors (TIS or PARIS). This is enabled by adding alignment markers around the circumference of the image field on the reticle. The measured reticle deformations are then fed to the system control network and dynamically corrected for by making use of the available manipulators in the scanner and the projection lens. Wafer-by-wafer reticle distortion measurements are performed to accurately capture the transient dynamics present in reticle heating during normal production lots. A new version of Reticle Heating Feed-forward Control (RHC2) is introduced that uses reticle-heating-induced deformation measurements over time and exposure sequence information to calibrate reticle-deformation-predictionmodels. These models are based on thermo-mechanical models that simulate reticle deformation under various exposure conditions and are applied in-line to the exposures to reduce intra-wafer overlay drift effects.
ASML’s 300mm scanner-systems are built on the TWINSCAN (XT/NXT) platform and yield high productivity levels for dry as well as immersion litho-scanners. NXT:1980Di immersion scanners yield productivity levels as high as 275wph while maintaining the overlay accuracy. The NXT:1980Di can be equipped with a new leveling mode that results in a significant reduction of the time that is spent on measuring the wafer focus height map. In the new leveling mode the focus height map is measured employing the full width of the level sensor and thereby minimizing the number of leveling scans. In this paper we describe the implementation of the LIL-method in the TWINSCAN platform design. Here, we report on the focus / leveling performance for both test as well as customer product wafers, and present a productivity outlook on the performance gain for a selected set of exposure use-cases.
As a result of the continuously shrinking features of the integrated circuit, the overlay budget requirements have become very demanding. Historically, overlay has been performed using metrology targets for process control, and most overlay enhancements were achieved by hardware improvements. However, this is no longer sufficient, and we need to consider additional solutions for overlay improvements in process variation using computational methods. In this paper, we present the limitations of third-order intrafield distortion corrections based on standard overlay metrology and propose an improved method which includes a prediction of the device overlay and corrects the lens aberration fingerprint based on this prediction. For a DRAM use case, we present a computational approach that calculates the overlay of the device pattern using lens aberrations as an additional input, next to the target-based overlay measurement result. Supporting experimental data are presented that demonstrate a significant reduction of the intrafield overlay fingerprint.
As overlay margin is getting tighter, traditional overlay correction method is not enough to secure more overlay margin without extended correction potential on lithography tool. Timely, the lithography tool has a capability of wafer to wafer correction. From these well-timed industry’s preparations, the uncorrected overlay error from current sampling in a lot could be corrected for yield enhancement.
In this paper, overlay budget break was performed prior to experiments with the purpose of estimating amount of overlay improvement. And wafer to wafer correction was simulated to the specified layer of a 2x node DRAM device. As a result, not only maximum 94.4% of residual variation improvement is estimated, but also recognized that more samplings to cover all wafer’s behavior is inevitable. Integrated metrology with optimized sampling scheme was also introduced as a supportive method for more samplings.
To accord with new requirement of securing more overlay margin, not only the optical overlay measurement is faced with the technical limitations to represent cell pattern’s behavior, but also the larger measurement samples are inevitable for minimizing statistical errors and better estimation of circumstance in a lot. From these reasons, diffraction based overlay (DBO) and integrated metrology (IM) were mainly proposed as new approaches for overlay enhancement in this paper.
In this paper we present the limitations of 3rd order distortion corrections based on standard overlay metrology and propose a new method to quantify and correct the cold-lens aberration fingerprint. As a result of continuous shrinking features of the integrated circuit, the overlay budget requirements have become very demanding. Historically, most overlay enhancements were achieved by hardware improvements. However there also is a benefit in the computational approach, and so we looked for solutions for overlay improvements in process variation with computational applications.
We report that, based on our experimental data, lens heating (LH) impact on wafer image can be effectively controlled by using a computational method (cASCAL) on critical device layers with no request on tool time. As design rule shrinks down, LH control plays a key role in preventing the image deterioration caused by the LH-induced wavefront distortion during exposure. To improve LH prediction accuracy, 3-dimension structure of mask stack (M3D) is considered in calculating the electro-magnetic (EM) field that passes through the mask for full chip. Additionally, lens specific calibration (LSC) is performed on individual scanners to take the lens-to-lens variation into account. In data comparisons, we show that cASCAL performs very well as an ASCAL substitute, and that M3D and LSC improve the LH prediction accuracy of cASCAL.
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