Proceedings Article | 22 February 2021
Wenzhan Zhou, Fang Wei, Yu Zhang, Jun Zhu, Chan-Yuan Hu, Kyoyeon Cho, Antonio Corradi, Kuo-Feng Pao, Vivek Jain, Abdalmohsen Elmalk, Sudharshanan Raghunathan, Stefan Hunsche, Robbin Zhu, Selena Chen, Luke Lin, Leon Liang, Lei Liu
KEYWORDS: Overlay metrology, Statistical analysis, Scanning electron microscopy, Metrology, Semiconducting wafers, Error analysis, Critical dimension metrology, Stochastic processes, Shape analysis, Image analysis
Edge placement error (EPE) analysis, which combines pattern variation data from single litho-process steps with overlay data from subsequent litho-process steps, has been well established as a key methodology to characterize the performance of complex semiconductor manufacturing processes. As critical dimensions shrink in new semiconductor technologies, process margins become tighter, and characterizing and monitoring EPE budgets becomes more important than ever to assess and maintain in-line process performance and yield. In this paper, we present SEM image contour-based EPE analysis and budget generation for a BEOL multi-patterning (LELE) layer. SEM contour analysis was previously shown to be a suitable method for pattern variability characterization, with the capability to capture not only pattern size, but also shape and local stochastic placement variations, and to provide statistical overlay margin estimates between separate device layers. In the current work, we also show that for a LELE process, contour analysis provides local overlay measurements and all inputs needed to generate the complete EPE budget breakdown. Multiple wafers from a device in production were provided after processing the second etch step of a metal layer LELE process. We acquire large field-of-view SEM images with a high-throughput e-beam tool (HMI eP5), sampled within die, across exposure field and across wafer in order to enable analysis of variability into global and local components. Pattern contours are extracted from individual SEM images, and contours are ‘stacked’ to identify specific locations of largest variability or smallest margin. While the images contain patterns from both processing steps, these can be uniquely distinguished after die-to-database alignment and labeled by mask ID, here 1st and 2nd litho-etch layers, respectively. In addition to size, shape and stochastic placement variations, we perform center-of-gravity analysis between patterns on the 1st and 2nd litho-etch layers. The latter reveals local on-device overlay variations that can be mapped across the measured wafers. The contour analysis therefore provides all information required for a thorough EPE budget breakdown, i.e. global CDU and local CDU for the most critical cutline locations, as well as overlay. Figure 1 shows the breakdown for one particular point of interest. We perform EPE budget analysis for multiple wafers, which can highlight wafer-to-wafer variations. This is a first step toward process monitoring, which would not only highlight process drifts, but also distinguish main contributors in order to aid in trouble shooting. KEYWORDS: pattern variability, pattern fidelity, contour analysis, edge placement error, holistic lithography, SEM metrology
